[Synthesis/STA] slack in Setup violation and slack in Hold Violation

Setup time equation and slack in Setup violation
Hold time equation and slack in Hold Violation
fix setup and hold violation
• [Synthesis/STA] fixing...

[@saravanakumar7290]

Great work brother!
Not sure why those 5 who disliked, even this kind of academic videos. If they don't want to watch they can simply skip, instead of giving dislike.

[@VLSI-learnings]

Thank YOU

[@A_yush_man]

Your explanation leaves no room for doubt in a concept. Please keep going

[@VLSI-learnings]

thanks.. keep watching my videos

[@swapnilvhatkar7753]

Very informative, now I got a clear picture of difference between setup and hold violation.

[@VLSI-learnings]

Thank you

[@TheYasaswy]

Thank you for such a nice description. It does help in understanding of concepts and also for cracking interviews

[@VLSI-learnings]

Most welcome!

[@shubhamnayak9369]

U have talent to explain difficult concepts in simple words

[@VLSI-learnings]

Thank you

[@vsgraju5650]

Please explain why we actually need setup & hold times.. unless that is clear there will always be confusion !!

[@akashwayal8797]

this is by far the best video for setup and hold violations!

[@VLSI-learnings]

Thank you

[@GK-yr7sx]

Clear explanation for setup and hold violations , Thanks sir

[@VLSI-learnings]

You are welcome

[@jayasameervarma5655]

How will D1 change, if tcq+tpd of FlipFlop 1 is less than its hold time ? Please explain

[@RohitPatel-er3qw]

Good explanation Sir. Thank you very much for the session.

[@VLSI-learnings]

You are most welcome

[@thejeshvenkata8694]

Awesome explanation, thanks

[@VLSI-learnings]

Thank you

[@taraldc]

Hi Sir.. There is a brightness variation in video recording, hence it is very difficult to watch, Can you please rerecord the contents.

[@VLSI-learnings]

I will try my best

[@deepakm3029]

Hold violation is not for FF1 it is for FF2!! (If it is for FF1 why would you add Tcombinational delay.)

[@VLSI-learnings]

ex FF1 hold window 1ns if clk-q delay is 0.5 and tcombo 0.2 ns then which flop is effected FF1 or FF2. draw the waveform and check

[@deepakm3029]

@@VLSI-learnings Yes Sir, wouldn't that be FF2!. Sir if it was for FF1 then why would Tcomb will be there in the equation(consideration) at all (I mean how can change in Tcomb effect hold time of FF1 at all)!

[@VLSI-learnings]

@@deepakm3029 1st you asked about "Hold violation is not for FF1 it is for FF2!! " I clarify that hold violation in FF1 not FF2.
2nd point " how can change in Tcomb effect hold time of FF1" hold time of any flop is fixed as per technology library . it that hold window time data must be stable . above example i provided it will cause hold violation in FF1.

[@deepakm3029]

@@VLSI-learnings Thank You Sir!

[@priyankasuru2451]

Sir, if D2 changes at hold window of Launch Flop, How hold violation occurs ,we need to consider if there is change in D1 right?

[@radheshyamsharma8994]

sir at time frame 14:00 shouldnt it be 1ns < Total delay < (4ns-1ns) ?

[@aswathyvasudev1772]

Good explanation sir

[@VLSI-learnings]

Thanks

[@Vishal-ux2ro]

if there is positive clock skew why holdtime increases

[@rowdyboysking7794]

Good sir,do more videos sir

[@VLSI-learnings]

Ok

[@AliMuhammad-sm9hx]

Excellent...

[@VLSI-learnings]

Thanks

[@obtron]

Sir for hold violation shouldn't we have to consider the Capture FF right? for eg:
if tcq1 =2 ns, tpd= 3ns, and thold2 = 6ns
before 6ns old data is overwritten by new data at (tcq1+tpd) 5ns so hold violation occurs for ff2.

[@VLSI-learnings]

ff2 hold will be calculated if ff3 involved

[@SatishSahuMKG]

Hi Sir could you share the link of full watch list of STA

[@jayanthilankala2504]

thanks for the video. There is some disturbance in audio.

[@VLSI-learnings]

Welcome

[@yashika7968]

Amazing 👌😍

[@VLSI-learnings]

Thank you! Cheers!

[@syedAli-kf6jx]

Hi Sir , what can we do if the path is fully optimize , no scope of further optimization, how we can fix setup and hold with clock push and pull

[@VLSI-learnings]

How to fix setup violation in other vedios please go through that vedio

[@sonalikasingh1395]

Sir, the time between launch edge and capture edge is defined by our operating frequency right!? And therefore always 2nd edge of the clock has to be the capture edge ideally right!?

[@VLSI-learnings]

yes Sonalika.

[@sonalikasingh1395]

@@VLSI-learnings Thnku sir😊

[@Naveenkumar-mj8eh]

Sir everything is good but ur camera is many times going to focus u thats y it is shaking screen every second that is not good to see else concept is good

[@VLSI-learnings]

I will do my best ..next time

[@pavanbhandari1177]

Good one...

[@VLSI-learnings]

Thank you 🙂

[@kavitha-tn6fj]

what type of mismatches we will get in simulation due to setup and hold violations?

[@VLSI-learnings]

setup and hold violations is exist in design In functional simulation we will not see any issue. In GLS you will see simulation mismatches

[@sugsatyam88]

Thanku sir ...

[@VLSI-learnings]

Welcome

[@arunraju6875]

Please do videos on latch based Timing.

[@VLSI-learnings]

Ok

[@seshadriy5133]

Why setup will check next edge and hold will check same edge

[@VLSI-learnings]

Yes good question... see there video full then you will understand the question

[@anands5543]

Sir delay will vary for both setup and hold in library files ? Like min and max according to that tool will calculate setup and hold violation ?

[@saivijayabhaskargade1528]

setup value depends on transition time of data/clk to that flop from previous logic cell . it varies from flop to flop , based on transition time.

[@VLSI-learnings]

Yes ..

[@Insideoperation]

kindly record your lecture in urdu/hindi. your English is very weak angrazo k chakkar ma hun ko be kuch sammaj nahi ati