What my lecturer could not make me understand easily, i just got the easiest lecturer that has made understood 100% for free. I'm grateful for this channel
I deeply appreciate that even this far into the lectures, you still go over the basic things like the k-maps instead of just assuming the viewer knows how to do it. It helps so much with conceptualization and I see almost nobody doing it, so thank you a ton.
You are actually working towards making our country developed by developing 1. the brains of so many students in digital electronics who cannot easily understand the concepts 2. mainly free of cost!. THANK YOU SIR.
This is one of the best TH-cam channels for studying digital electronics. It clears all my concepts and makes learning so easy. Good going Neso Academy!
not only digital electronics but all subjects whatever they have covered completely but some of their playlist are not completely free if they can make that free too then i don't think they have competitor in youtube at least for engineering student
Thanks to you, sir, I have cleared my internal examinations of Digital Electronics. Thank you very much. Shout out to Neso Academy! Keep up the good work.
Hello everyone :) i believe i how found the explanation to the confusion we are all sitting with. How do we get 0 and 1 as Qn in the truth table's two middle cases.? First, what we must understand is that Qn represents the value of Q in a Nand-SR flip flop. (Q bar) is not represented in this truth table example as it is not relevant in some sence. Next, we must for ourselves try to visualize the Q output. First, let's put: Clock = 1, S=0, R=1. through the first nand gate at the top, (in previous lecture) we take 1 and 0 as inputs and get the S* as 1. For clock and R as inputs we get 1,1 which is 0 (according to our nand-gate truth table. so now we have S* as 1 and R* as 0. If we try to remember the SR-latch walkthrough he did a couple of lectures ago, we know that whenever S is 1, then Q is automatically 0, and when putting that input into the bottom nand-gate with R* then we get 1. so now we have S = 0, and R = 1. However, as mentioned just before, Qn represents the Q, not Q complement. So Qn represnets the Q, which is 0. therefore we put the 0 into the truth table as the value of Qn. For the third case where S = 1 and R = 0, (clock is ofcourse 1) Then the top nand-gate resolves into 1*1 = 0 = S*, and the bottom nand-gate resolves into 1*0 = 1 = R*. so whenever Reset is 1, then (Q compliment) is 0. and when you use 0 as an input for the top NAND-gate with S* then you get 1.. Again, it is very important to remember that Qn represents Q in our Sr flip flop truth table in previous lecture, so (Q compliment ) which is 0, is not included. So basically if you sit down, draw out the SR flip flop sequential circuit with control input as clock, and take clock as 1, and try both: S = 0, R = 1 S = 1, R = 0 Then you will get Q as Q = 0, (Q Bar) = 1 Q = 1, (Q Bar) = 0 But Qn again represnets Q, so the answer for case two would be: Case 2: 0 Case 3: 1. I apologize if i said the same words too many times :) but i don't want to loose anyone :) on beforehand :) thank you :)
I love you! Sir, you've managed to explain everything in such a simple and clear way, I'm so so grateful! Whatever takes my uni professor an hour to analyze (and confuse us even more), can be found in a ten minute video of yours. I vow to thee!!
I have a sequential logic exam today and was looking for that EXACT explanation for hours. The learning materials for sequential logic nets, we got from our professor, listed an excitation table for RS-flipflops and other logic operators. But nobody ever mentioned what an excitation table actually was?! NOWHERE and I repeat NOWHERE on the web could I find an explanation. Even the English Wikipedia article on excitation tables gives an explanation in words as to how one gets to an excitation table that´s about two sentences long. Of course that didn´t help me. THIS is the shit. This is what I was searching for. I could hug and kiss this man. God bless him.
I just realized that i have wasted money behind varsity .. Belongs full semester i didn't even understand anything but two days before of semester final exam i have completed my full course with the help of your video ..
Thanks a lot for such a good explanation in such simple way.... thumbs up... your way of breaking the long lecture in to smaller pieces is really impressive and understandable..
Hello sir in the previous you have explained sr latch with help of NOR AND NAND GATES there you have used NAND gate of I'm not wrong...and for input 00 you have written NO CHANGE (MEMORY) BUT for NAND GATE it is NOT USED..... You have said that NAND and NOR are opposite .....THANQ....SIR FOR EXPLAINING THE CONCEPTS IN DETAIL.....
First of all thank you so very much for this fantastic presentation. However I have 1 question left that is still puzzling me: why did you mark the invalid cases as "don't cares"?
it is so simple bro-that is invalid case-thus we can't determine the exact output for that case-but it should be of either 0 or 1-thus sir marked don't care
Thank you so much first time i understood flip flop properly. I had hard time understanding flip flop throughout my engineering but finally i got everything. Just wanted to know why we made this different tables. What are there uses i have completed all the videos till now may be i will understand this in later videos and if not please answer. Thanks a lot
How did you give the value for Q(n+1) when the values of S and R are 0,1 and 1,0 as 0 And 1?? Thanks in Advance.Your Lectures are very Nice and Helping!!
As this is a NOR SR Flipflop, we know from NOR SR Flipflop truthtable, when clk=1, S=0, R=1, Q=1 So here Q+1= 1+1=0. Similarly incase of NOR SR Flipflop when clk=1, S=1, R=0, Q=0 so here Q+1= 0+1=1. [I guess Q and Qn are same thing, and Q' is neglected]
This should be considered a public service. I'm so grateful for the work of this Channel.
Yes, friend he had nicely explained the concepts....
9 years old class still has the best quality ❤
What my lecturer could not make me understand easily, i just got the easiest lecturer that has made understood 100% for free. I'm grateful for this channel
Brother, you explain digital electronics as if you are the one that develop flipflops and latches.
What a great job!
I deeply appreciate that even this far into the lectures, you still go over the basic things like the k-maps instead of just assuming the viewer knows how to do it. It helps so much with conceptualization and I see almost nobody doing it, so thank you a ton.
You are actually working towards making our country developed by developing 1. the brains of so many students in digital electronics who cannot easily understand the concepts 2. mainly free of cost!. THANK YOU SIR.
Yes, he had nicely explained the concepts....
This is one of the best TH-cam channels for studying digital electronics. It clears all my concepts and makes learning so easy. Good going Neso Academy!
Yes, he had nicely explained the concepts...so you are absolutely right.....
not only digital electronics but all subjects whatever they have covered completely but some of their playlist are not completely free if they can make that free too then i don't think they have competitor in youtube at least for engineering student
Thanks to you, sir, I have cleared my internal examinations of Digital Electronics. Thank you very much. Shout out to Neso Academy! Keep up the good work.
Yes, friend he had nicely explained the concepts....
I declare u the next recipient for noble prize
Yes, friend he had nicely explained the concepts....
😂
Hello everyone :) i believe i how found the explanation to the confusion we are all sitting with.
How do we get 0 and 1 as Qn in the truth table's two middle cases.?
First, what we must understand is that Qn represents the value of Q in a Nand-SR flip flop.
(Q bar) is not represented in this truth table example as it is not relevant in some sence.
Next, we must for ourselves try to visualize the Q output.
First, let's put:
Clock = 1, S=0, R=1.
through the first nand gate at the top, (in previous lecture) we take 1 and 0 as inputs and get the S* as 1.
For clock and R as inputs we get 1,1 which is 0 (according to our nand-gate truth table.
so now we have S* as 1 and R* as 0.
If we try to remember the SR-latch walkthrough he did a couple of lectures ago,
we know that whenever S is 1, then Q is automatically 0, and when putting that input into the bottom nand-gate with R* then we get 1. so now we have S = 0, and R = 1.
However, as mentioned just before, Qn represents the Q, not Q complement.
So Qn represnets the Q, which is 0. therefore we put the 0 into the truth table as the value of Qn.
For the third case where S = 1 and R = 0, (clock is ofcourse 1)
Then the top nand-gate resolves into 1*1 = 0 = S*, and the bottom nand-gate resolves into
1*0 = 1 = R*. so whenever Reset is 1, then (Q compliment) is 0. and when you use 0 as an input for the top NAND-gate with S* then you get 1..
Again, it is very important to remember that Qn represents Q in our Sr flip flop truth table in previous lecture, so (Q compliment ) which is 0, is not included.
So basically if you sit down, draw out the SR flip flop sequential circuit with control input as clock, and take clock as 1, and try both:
S = 0, R = 1
S = 1, R = 0
Then you will get Q as
Q = 0, (Q Bar) = 1
Q = 1, (Q Bar) = 0
But Qn again represnets Q, so the answer for case two would be:
Case 2: 0
Case 3: 1.
I apologize if i said the same words too many times :) but i don't want to loose anyone :)
on beforehand :) thank you :)
thaks dude
Thanks in some words just ignore q bar right,and just compare the 3rd case for not used
so basically Q = Qn
Sir Q is present state but Q(n+1) is next state so how Q=Q(n+1) ?
Thanks Buddy!!
I love you! Sir, you've managed to explain everything in such a simple and clear way, I'm so so grateful! Whatever takes my uni professor an hour to analyze (and confuse us even more), can be found in a ten minute video of yours. I vow to thee!!
Hello ....??
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
I have a sequential logic exam today and was looking for that EXACT explanation for hours. The learning materials for sequential logic nets, we got from our professor, listed an excitation table for RS-flipflops and other logic operators. But nobody ever mentioned what an excitation table actually was?! NOWHERE and I repeat NOWHERE on the web could I find an explanation. Even the English Wikipedia article on excitation tables gives an explanation in words as to how one gets to an excitation table that´s about two sentences long. Of course that didn´t help me.
THIS is the shit. This is what I was searching for. I could hug and kiss this man. God bless him.
Yes really nice explanation......
Given Rs 50 via UPI , a small contribution for the great service u do , y'all should do same !
You a life saver brother you know that right?
value of s= Qn+1
value of r = Qn+1 bar ...using 4 cells k map
Each video so far was above average educational quality.
Concise and right length.
Thx
Absolutely right....
I am watching this video at 1:12 am
and I have my semester exam at 9:00 am. God help me and bless this man
Thank You So much for such a great and simple lecture. It's sequential way of teaching which is very easy to understand.
its 2020 ,these lectures were posted 5 years ago, but still help full. may God Bless You.
Check out 2024 - it's still saving lives
I just realized that i have wasted money behind varsity .. Belongs full semester i didn't even understand anything but two days before of semester final exam i have completed my full course with the help of your video ..
You are the Leonard for Logic Design subject.
Thanks a lot for such a good explanation in such simple way.... thumbs up... your way of breaking the long lecture in to smaller pieces is really impressive and understandable..
Tomorrrow is my exam! And this helped me alot ... Thanku very much 😋
awesome explanation sir...now I am able to draw flipflops and its table on my own...THANK YOU...
thankuuu so much.❤..mam ne krwaya tha class me pr mai bhul gyi thi..and u remind me the whole again..thankuu..your explanation is really good😊😊
Yes, friend he had nicely explained the concepts....
Neso is god of digital electronics
This should be considered a public service
This chanel not only provides digital electronics but its also provides the best lectures of engineering subjects
Well done👏👏
Great stuff thank you. If anyone is having issues, look at the previous videos. Does a great job explaining everything
Yes his videos are really helpful
Explanations are clear, pedagogy is top notch thanks from France =)
Absolutely correct.....
I am studying every subject form this channel.
Sir the teaching is so so amazing keep goin like this I really enjoyed learning this way thank u so very much it helped my exams 😊🙏
Roll number in username 👁️👄👁️
Dear, don't put your Roll no in your username. Chances of it getting manhandling increases
Best teacher for Digital electronics
Absolutely right....
I'm watching this at 12:06a.m. because i couldn't understand the class at all. Thank you Indian guy
Yes, friend he had nicely explained the concepts....He is an indian?
i literally love youuuuu sooo much.thanks for making concepts this easyyyy
I guess this charateristics table is When we used NOR gate, right??
as u said when s=r=0 then memory
this guy xplain it way simplier 👍🏻👍🏻👍🏻
Neso Academy.. Oh Thank you so much... I understand it very clearly.... Thank you ...
Thank you sir 🙏 All videos are very helpful and very well presented 🙏🙏
Thank you sir for excitation table🙏🙏🙏
Really puzzle breaking tutorial for me on these concepts. very nice.
Yes, friend his explanation is really helpful
Thank you
Neso Academy.
Thank you so much bro❤❤❤🎉
thanks alot sir , your lectures are life savor :): ))
Thanks a lot due to this i can understand very easily
That was very helpful. sir. excellent explanation.
Thaaaaaaaku so much sir kitta bhi thanks bolu kaam h apke liye to
Yes, really nice video.....
Very helpful. Love you for these tutorials. Thank you
Very nice explanation
great work sir!!!
I truly respect u...!
Very good explanation so easy to understand thanx for this video👍
Yes really nice videos and nice explanation....
Very clear explanation...
Neso academy you're the best
Thank you Neso
really its so clear explanation, you are the best tauter
A saviour have born to slay .. Slay this mighty subject 🔥🔥🔥
good explanation sir. Why do you consider invalid case as don't care?
Thank you for the lesson.
Great teaching ❣️
Good presentation 👍...i really got it
nice one !! help me to understand more about this chapter for my final exam...
Hello sir in the previous you have explained sr latch with help of NOR AND NAND GATES there you have used NAND gate of I'm not wrong...and for input 00 you have written NO CHANGE (MEMORY) BUT for NAND GATE it is NOT USED.....
You have said that NAND and NOR are opposite .....THANQ....SIR FOR EXPLAINING THE CONCEPTS IN DETAIL.....
well explained thank you so much👍👍
Excellent explaination
Thank u so much.. U r an amazing teacher
In excitation table, S = Q(n+1) and R = (Q(n+1))'
Yes
Next state concept is really typical....explain it clearly
your are the best explainer
very good videos. ...it helped me lot to score good in exams. thanks! !!
+Jaya Sharma Mumbai university???
no
no
*awkward*
Thank you very much sir🥳🥳🥳🥳
First of all thank you so very much for this fantastic presentation. However I have 1 question left that is still puzzling me: why did you mark the invalid cases as "don't cares"?
same question
it is so simple bro-that is invalid case-thus we can't determine the exact output for that case-but it should be of either 0 or 1-thus sir marked don't care
Thank you, sir.
Thank you 🛐
oh man this channel is so helpful!!!
Yes, friend he had nicely explained the concepts....
Thank You Sir 🙏🤲❤️
top quality teaching
Exactly....
Thanks Maya ❤️👍
Maya?
great ......... u save my day sir
Thank you so much first time i understood flip flop properly. I had hard time understanding flip flop throughout my engineering but finally i got everything. Just wanted to know why we made this different tables. What are there uses i have completed all the videos till now may be i will understand this in later videos and if not please answer.
Thanks a lot
Hello Alka, I hope you understood the concept clearly.....
i am watching this video a day before semester exam and i have the whole syllabus to cover..... whole!!!!
Oh my god....
Thank you so much, you're doing a really instrumental work for students
Yes, friend he had nicely explained the concepts....
OMG! Great lecture.
Yes, friend he had nicely explained the concepts....
thanks NESO
Sir, we need lectures on power electronics
THANK YOU SO MUCH
You are the best!
Yes absolutely right....
Super very useful sir
How did you give the value for Q(n+1) when the values of S and R are 0,1 and 1,0 as 0 And 1?? Thanks in Advance.Your Lectures are very Nice and Helping!!
Yeah that's what I also wanna know !!
@@spacepacehut3265 and did you get it?
@@spacepacehut3265 Same here. If you know kindly tell me too
As this is a NOR SR Flipflop, we know from NOR SR Flipflop truthtable, when clk=1, S=0, R=1, Q=1 So here Q+1= 1+1=0. Similarly incase of NOR SR Flipflop when clk=1, S=1, R=0, Q=0 so here Q+1= 0+1=1.
[I guess Q and Qn are same thing, and Q' is neglected]
Thank you sir
AMAZING 😍. SO THANKFUL 😇
Thank you
Thank uhhhhh so much sir 🙏🙏
Wow its really very very good.....
Best video 👍👍👍👍👍👍👍👍👍
Very helpful. Thanks
Very helpful channel .
Yes, friend really helpful
Thank you so much for such an amazing content I have a doubt that why you use that invalid case as don't care in k-map
Yes, friend his explanation is really helpful
Sop for s = Qn+1
Sop for r =( Qn+1)'
Is this right ? , Done using 2 variable k map.
thank you so much