This free education is much better than the college class I am paying for. I understand the concepts after watching your short videos once or twice. I spend way more time than that reading a textbook and watching my university's videos without understanding. THANK YOU so much!
Within few days I covered most parts of your lectures and they were really helpful. I had my examination today and it went smoothly because of this channel. Thank you for saving me a repeat! Now gonna watch your C programming playlist.
if i had watched these lectures while taking CS-303 course i would take an easy A instead of B+(i even copied in exam :D) :/ shame i struggled with this easy stuff. Very good content. i started from 40. vid and now thats the 146. vid. it took 2 days to finish almost all content of cs-303 although it is 6:40 in the morning and i havent slept yet :D
A very big thanks to the sir who presented this module with much clarity......I had struggled a lot in understanding the concepts of FF before . but nw its very much clear for me... thnk u sir......
what an amazing video!, first video I've watched from you, understood it instantly. Not even my native language, but I prefer to continue with your videos rather than using german videos. very helpful!
Buti pa dito nagtuturo. Mga teacher dito sa pilipinas nagbibigay lang ng module tapos swesweldo ng 40k. Pag nagchat ka sakanila sasabihin tignan yung explanation sa module. Ang galing ah. Sila pa mga teacher ang welga ng welga na taasan sahod nila hindi naman nagtuturo
A small confusion, I assume you explained D latch in this video and not D flip flop. The circuit is still level-triggered. Using lathes and flip-flops alternatively causes some confusion.
In 3 and 4 case R and S are inverted but what about the second case,, in that both are zero while the clock is one, why you didnt used that , what if we have to give 0 input on both R and S? Plz explain sir
what is the difference between D latch AND D flip flop? Truth table for both are the same there is only change of En and CLK So how do they differ from each other? same is the case for SR LATCH AND SR FLIP FLOP. Can you please explain these?
If enable in present, and it is operational for the whole circuit, then it is called latch. If clock is present and it is operational for the whole circuit then it is called flip flop.
Does it mean that we don't have a " memory" condition with D flip flop? Will it not act as a memory ? What are its Functionalities then ? Please Do Reply Thanks :)
Well the memory case for this will be when the clock is low i.e 0..... Because if u see carefully the memory case arises under two circumstances 1) when the clock is low 2) when both the inputs are low..... So in this d ff case we are not using the two low input case
It may be called a Data flip-flop because of its ability to ‘latch’ and remember data, or a Delay flip-flop because latching and remembering data can be used to create a delay in the progress of that data through a circuit. To avoid the ambiguity in the title therefore, it is usually known simply as the D Type.
Sir I have a doubt..As u said that s and r are always complement to each other so we need only one input in d flip-flop...But if we consider the truth table of s-r flip-flop there is a case where s and r are booth equal to zero and we get memory as output..So if we dnt use another input in d flip-flop then this mentioned case will not be valid and hence the flip-flop can't store the previous data..So how can we store data in d flip-flop?
This free education is much better than the college class I am paying for. I understand the concepts after watching your short videos once or twice. I spend way more time than that reading a textbook and watching my university's videos without understanding. THANK YOU so much!
1 year after that u made a 4-bit microprocessor want an improvement
Yes seriously man
True bro
I also have same opinion
For real bro,we all are wasting our time coz of college attendence issue
Within few days I covered most parts of your lectures and they were really helpful. I had my examination today and it went smoothly because of this channel. Thank you for saving me a repeat! Now gonna watch your C programming playlist.
It took me 2 days to complete the whole Playlist in 2x
This guy is really a life saver. Thanks a lot man for giving this high quality content for free.
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
2:18 "I need only a single input that is my D". hahah
... if only we could survive with that 'only D.' :D
xd
legend
@3:02 "and take my c(L)ock out"
My Ds always flipping and flopping
if i had watched these lectures while taking CS-303 course i would take an easy A instead of B+(i even copied in exam :D) :/ shame i struggled with this easy stuff. Very good content. i started from 40. vid and now thats the 146. vid. it took 2 days to finish almost all content of cs-303 although it is 6:40 in the morning and i havent slept yet :D
damn slow down is good too to master all those element
sabancıda hoca olsaydım yakmıştım şimdi yağız :D
sınava 1 gün kala kesfettigim için bende aynı şeyi düşünüyorum
A very big thanks to the sir who presented this module with much clarity......I had struggled a lot in understanding the concepts of FF before . but nw its very much clear for me... thnk u sir......
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In 2024 motorola phone and zomato ads are annoying 😅
😂
I know right
Real bro
Scaler ad is so annoying
what an amazing video!, first video I've watched from you, understood it instantly. Not even my native language, but I prefer to continue with your videos rather than using german videos. very helpful!
Please keep silence 🔕 🙏
amazing explanation...........Love you much much more than my girlfriend because i got it when i needed it the most.
😂😂
lmao
😂😂🤣🤣🔥
your girlfriend have seen this :))
🤣🤣🤣
Thank for your making this video! I understand D-flipflops now; my textbook couldn't get me there.
Salute to neso for helping free of cost
Sir your teaching is really awesome , thanks sir for these types of video.
This guy is really a life saver
Thank you! This just made my 15 lecture slides make sense :)
I read in book that for converting D flipflop to SR flipflop there will also be 2 NAND gates also with sr flipflop
Hi
Yes because in SR latch memory is there....and 2 nand gates are there becz they are clk SR latch
time flips when i listen to your voice sir
need more videos from coding
Probably the best explanation videos on youtube!
Thank you for these lectures.
Your explanation is amazing.
Thank you sir.
you make Turkey proud thxxx
nalaka
Thank you so much, Sir.
Thank you my Indian friend, baraka Allahu feek !
Man, you are amazing!!
I can't thank you enough for your informative lessons
This was soo helpful! Thank you!
Clear explanation.. Thank you sir
Thanks for Explaining in this details...This will Help me a lot....!
Sir lekin we didn't talk about the case when
Clk=1 , S=0 ,R=0 .
Sir your classes are so helpful
Ham sirf degree aur exam k liye college me fees dete hai
Padhai to hm TH-cam se krte hai 😅
you are a life saver
Woow d flip flop is easy.... Thankyou neso
thank you master i love you way to explain things :)
Well executed explanation.
I've started to like your videos even before watching them :p
They are that good.
very good explanation sir!!!!!!!!!!!!!!!
yes
Thank u so much your explanation is the best.
Suggestion:- The lecture no. must be included in the video title.....so that all the videos will be arranged after downloading for offline use.
thank you very much sir
Thank you very much sir🥳🥳🥳🥳
Best explanation ever . thank you ever so much
Can you explain to me what qn+1 is? You never explained the context of that variable in your SR flip flop video.
Qn+1 is the present input, because it is the next input after your past input (Qn)
@@COVERMAN55555 Or you can say that Qn is the present state and Q(n+1) is the next state
.
Well explained sir
So What happens to the s=0 and r=0 of the SR Flip flop ? Why we are ignoring that in D-flip flop?
that dosent exist in d flip flop
It is not ignored I think, it will provide a memory output/previous output
you made it so so simple amazing and thank you
all videos is very helpful
Letter 'D' in D-Flip Flop actually stands for 'Delay', not 'Data'.
Yes
thank you♥♥
sir ur videos r so helpful keep up the good work
It's like a latching inverter pretty much, with 2 complimentary outputs
Thanks Sir 😃😃
Thank you, that is super understandable!!
Is the D flip flop the same thing as the gated D latch?, because in my textbook i have exactly what you have but its under gated D latch.
same but gated d latch has enable input and d flip flop has clock pulse
Thank you so much bro!!!
I watched this vedio for my lcd exam now i watching for supplymentary😁
You help me a lot
thank you sooo much it helps me very much
I wish that you must make videos like this.
no one -
neso academy intro - randon african safari music
Sir,
Please reply to this doubt
When you said 0 stored and 1 stored, but which output actually is considered in TT 4:35. Q or Qbar
What program do you use to write these lessons
great job thanks
Neso academy instructional way is supper
your lecture is interesting,kind and easy to understand! Thank you so much.
Buti pa dito nagtuturo. Mga teacher dito sa pilipinas nagbibigay lang ng module tapos swesweldo ng 40k. Pag nagchat ka sakanila sasabihin tignan yung explanation sa module. Ang galing ah. Sila pa mga teacher ang welga ng welga na taasan sahod nila hindi naman nagtuturo
Where is this guy come from? this is so helpful thank you very much
India
may god bless you sir!!!!!!!!!!!!!!!!!!!!!!
A small confusion, I assume you explained D latch in this video and not D flip flop. The circuit is still level-triggered. Using lathes and flip-flops alternatively causes some confusion.
but what about the other Q output? the one with a short line on it
is it D flip flop always using SR flip flop, or is there another way ?
Thanks for the help. I love that your presentation is clear.
THANK YOU
Thank you sir
In 3 and 4 case R and S are inverted but what about the second case,, in that both are zero while the clock is one, why you didnt used that , what if we have to give 0 input on both R and S? Plz explain sir
where is the intro song from?? i recognize it but can't remember
Thank you!
at 03:56
in diagram of D flip flop at output it shown Qn but in truth table for D flip flop it is written Qn+1 w WHY?
Because Qn+1 is the next state and Qn is the present state
please provide videos concerning Basic Telecommunications
thank u .....you have explained it in a very simple way
what is the difference between D latch AND D flip flop?
Truth table for both are the same there is only change of En and CLK
So how do they differ from each other?
same is the case for SR LATCH AND SR FLIP FLOP.
Can you please explain these?
If enable in present, and it is operational for the whole circuit, then it is called latch. If clock is present and it is operational for the whole circuit then it is called flip flop.
Okay thanks .
Enable only fr positive condition, while clock fr both
Does it mean that we don't have a " memory" condition with D flip flop? Will it not act as a memory ? What are its Functionalities then ?
Please Do Reply
Thanks :)
i have the same question
maybe u can answer me now ? it's 2 years :D
Well the memory case for this will be when the clock is low i.e 0..... Because if u see carefully the memory case arises under two circumstances 1) when the clock is low 2) when both the inputs are low..... So in this d ff case we are not using the two low input case
we can have that while the clock remains off, which will make s*=1 and r*=1. Thus we will be having the previous state.
Sir then what about the 00 condition which is not invalid in the truth table ....then how can we use only one input?? Pls do reply sir
These saved my life, thank you very much! Taking 152 right now, if anyone from my school are watching these they would know XD.
Thanks a lot!
Superb
Sir , what if we have S=0 and R=0 as input to D flip-flop ?
no change
In D flip flop there's no S & R. Rather there's D(a single input).
Hope you get it now!
Thanks a lot
Sir in my college it has told that D stands for delay and you told that D stands for data.
I am confused about it sir please clear my doubt???
It may be called a Data flip-flop because of its ability to ‘latch’ and remember data, or a Delay flip-flop because latching and remembering data can be used to create a delay in the progress of that data through a circuit. To avoid the ambiguity in the title therefore, it is usually known simply as the D Type.
Sir what is racing and how racing occurs pls explain in basic form so that we can understand easily
What abt s=0 and r=0 ??
Sir, in this lecture it is not clear SR flip flop is made by used which FF (NAND or NOR).Can we make a D FF by using SR FF(created by NAND Gate)
what is Next state and present state and what is the use of it??
Tysm❣️
I have a doubt
You told that s and r are complement to each other.
But what about 0,0?
Krishna Priyatham even that combination is nit possible as tgere is a not gate connected to one of the inputs
thank you so much, sir!!!!! really really useful!!!!!!!!!!🤞🤞🤞🤞🤞🤞🤞🤞
thank you
In this presentation how to find value of Qn+1 in TT for SR Flip-Flop
sir please do video on D latch
Sir I have a doubt..As u said that s and r are always complement to each other so we need only one input in d flip-flop...But if we consider the truth table of s-r flip-flop there is a case where s and r are booth equal to zero and we get memory as output..So if we dnt use another input in d flip-flop then this mentioned case will not be valid and hence the flip-flop can't store the previous data..So how can we store data in d flip-flop?
you can store data onlt 1,0 or 0,1 case. Others is not used in d flip flop.
Can you please upload a video on "D Type positive-edge-triggered" flip flop using three SR latch?
Thanks