Lecture 31: Latches and Flip-Flops (Part I)

[@mofijulsk2527]

Thank you very much ❤️

[@sujal_jadhav1344]

Thanks a lot sir...❤

[@siddarampatil857]

Tq sir it helped me

[@shubhambhardwaj2626]

Sir in Gated SR latch using NAND Gates
if E=0 You said it doesn't matter what the value of S and R is(Don't care)-Output will not change
but when E=0 S'=R'=1 which is invalid combination and the output will depend on the speed of the gates(race around condition)
that means the stored element will either be a 0 or 1 (Q=0,Q'=1 or Q=1,Q'=0)
but in the state table you mentioned No change. Why ?

[@SahilSingh-yw9mg]

referring to 25:12 . Hey if E=0, S'=1 as well as R'=1 or you can say S & R in the original non-gated latch are 0 which is perfectly fine.

[@vinodgill508]

Bro, for NAND SR latch state table is different, here S=1, R=1 is the hold state..

[@SurajSingh-hs3pi]

❤️❤️

[@bethamanjunath910]

06:50 _until the power is on_ can any one elaborate on that. I'm new to electronics. I can't see any external source there. Where is the on off situation coming from.

[@sreekantasai1675]

We use a light sensor

[@arkapravaghosh275]

Thanks for not adding subtitles.