In class for more than 90 minutes but did not understand at all. This guy came in and explain in 10 minutes and fully mind blown. What a legend. You truly deserved a like and subscribed my friend
Just think about it for a second: IF all those "professors" with their "ceaseless classes" were able to actually teach you stuff then they would become redundant. It's their bread and butter to confuse you by overloading with nonsensical garbage 🤣
Enable input is another input to the latch. When this enable input is high ( or low, depending on the latch configuration) then and then only, the latch will respond to the input. If enable input is not high, then latch will retain its previous state. I hope, it will clear your doubt.
9:10 even though we input clock signal to gated latch still it going to be as a level triggered latch right ! can't be edge triggered. so how it can be become a flip flop ?
Hi, dear channel owner; yesterday, I bought an advance membership for the channel, hoping to find all lecture notes as written in the membership instructions. However, now I see that only a few notes are available. Is it possible to post the rest of the notes for sequential circuits? It would be really nice if possible:)
Yes, I can provide that. But it will take little time. ( week or so). The thing is when I provided the notes, I didn’t get much response from the members.I even did the poll and asked for feedback. So, I didn’t publisher further.
@@physics2773 because output can look up to an input only when high enable. As you see there is low enable so output could see what is in input and just continued how it was doing
sir if flip flop is just a latch with clock signal in the enable signal, how it becomes edge triggered when latch is level sensitive, i am very confused please help
Its not only a clock signal. It also consists of clock transition circuit. I have already explained it at 9:07. Please watch the entire video, you will get it. And in the subsequent video, I have also explained the clock transition circuit. Please go through the sequential circuits playlist on the channel. You will get the videos in a sequence. If you still have any doubts, then let me know here.
@@ALLABOUTELECTRONICS th-cam.com/video/CiS7N2C8-Ik/w-d-xo.html In this video at 6:04 you show clock transition circuit but don't explain what it is the whole video. I actually understood it from other sources that sr flip-flop is made by connecting two sr latches together. I think that this important information should be provided at very starting rather then in very later videos(not still sure in which video you have explained😶🌫️) Btw didnt expect you will reply(and also soo fast). Your series helped me lot during this semester. Best one of YT. ThankYou very much
In this video also I have stated the same. Please check around 3:56. And please mention about the video, you are referring to, so that I can clear your doubt.
Timestamps:
0:00 Introduction
1:01 What is Latch? What is Gated Latch?
4:52 What is Flip-Flop? Difference between the latch and Flip-Flop
In class for more than 90 minutes but did not understand at all. This guy came in and explain in 10 minutes and fully mind blown. What a legend. You truly deserved a like and subscribed my friend
Just think about it for a second: IF all those "professors" with their "ceaseless classes" were able to actually teach you stuff then they would become redundant. It's their bread and butter to confuse you by overloading with nonsensical garbage 🤣
@@b213videoz true
College sucks :(
Finally after 2 weeks I managed to find a video clearly explaining the difference between gated latch and flip-flop 😊
This guys channel is carrying an entire generation of electrical students
and computer science students in computer architecture lol
Thanks for saving my semester
This guy is elite🙏🏻
Thank you so much for your excellent videos! Keep making them, you will be helping so much more people and one day this channel will go big😍
Bro ur lesson saved me ♥️ for ya
Very well explained
2:58 what so thr difference between input and enable input?
Enable input is another input to the latch. When this enable input is high ( or low, depending on the latch configuration) then and then only, the latch will respond to the input. If enable input is not high, then latch will retain its previous state. I hope, it will clear your doubt.
love your elplaination sirji
9:10 even though we input clock signal to gated latch still it going to be as a level triggered latch right ! can't be edge triggered. so how it can be become a flip flop ?
Hi, dear channel owner; yesterday, I bought an advance membership for the channel, hoping to find all lecture notes as written in the membership instructions. However, now I see that only a few notes are available. Is it possible to post the rest of the notes for sequential circuits? It would be really nice if possible:)
Yes, I can provide that. But it will take little time. ( week or so). The thing is when I provided the notes, I didn’t get much response from the members.I even did the poll and asked for feedback. So, I didn’t publisher further.
Can you please specify the topics.
Thank you so much sir for the great explanation and keep doing sir
4.40 you said that it continued with same why it continued it has low enable then pls explain doubt
4:40 The last high in output continued even when there was low signal in enable. Why??
@@physics2773 because output can look up to an input only when high enable. As you see there is low enable so output could see what is in input and just continued how it was doing
Good explanations with visuals
big thanks man, you helped me so much
aap hi humare guru ji ho electronics mai 🥲
Really very informative 👍🏻
great explanation!
Thank you for so informative videos.
sir if flip flop is just a latch with clock signal in the enable signal, how it becomes edge triggered when latch is level sensitive,
i am very confused please help
Its not only a clock signal. It also consists of clock transition circuit. I have already explained it at 9:07. Please watch the entire video, you will get it. And in the subsequent video, I have also explained the clock transition circuit. Please go through the sequential circuits playlist on the channel. You will get the videos in a sequence. If you still have any doubts, then let me know here.
@@ALLABOUTELECTRONICS th-cam.com/video/CiS7N2C8-Ik/w-d-xo.html
In this video at 6:04 you show clock transition circuit but don't explain what it is the whole video.
I actually understood it from other sources that sr flip-flop is made by connecting two sr latches together.
I think that this important information should be provided at very starting rather then in very later videos(not still sure in which video you have explained😶🌫️)
Btw didnt expect you will reply(and also soo fast). Your series helped me lot during this semester. Best one of YT.
ThankYou very much
What is the difference between trigger and clock signal
Clock signal means the output goes low and high so many number of times as per frequency
99.99% of viewers: this is better than my professor
0.001% of viewers: im 10 why am i here
thank you so muchhhhh
crystal clear explaination👌🏻
thank you sir
in the previous video about gated sr latch u said when enable is low it retains previous state
In this video also I have stated the same. Please check around 3:56. And please mention about the video, you are referring to, so that I can clear your doubt.
@@ALLABOUTELECTRONICS thank you sir i made a mistake in understanding
Genuine doubt and also nice explanation ❤
Thanks very much bro I am from Egypt
yo hooo iam from Egypt too lol, no one explains this shit clearly here
@@abdullahahmed1673 الدنيا صعبة يخويا ربنا يسهل
You're a G my friend!
how gated latch can be used as synchronous memory element by using clock signal
i think it will become synchronous sequential circuit not synchronous memory element once reply
I have already explained that in this video.
Here is the link : th-cam.com/video/CiS7N2C8-Ik/w-d-xo.htmlsi=a2wgwLmh5MMgqzQj
besttttt
yess!!!
goated
hai
Sar Hindi me to samjha dete