madam thank you so much , i have been watching your tutorial both digital and control systems, they are very clear and educative, you the best from Kenya
Mam. Can we give the op of Q1 to as clock ip to the next flipflop. If we give the op of complement of Q1 as clock ip then wt is the difference between this two can u say mam plz
The principle is for flip flop 1 u need external clock pulse , and for flip flop 2 it takes the output of flip flop 1 as clock pulse , This type of counter is known asynchronous counter !!
Can we give the out put of Q1 as clock ip to the next flip flop and why should we give the complement of Q1 as ip to the next flipflop can u say the difference between this two?
Check out Digital Electronics courses at: bit.ly/3aIM1ur
Use coupon "TH-cam12" to get FLAT 12% OFF
Who else is watching this a day before your exams😂
Abhi 2 ghante bad exam h
Kal exam h
☝️
Few hours
15 mins bad hain exam 10.30 baje
U deserve the global prize for making me to pass the university exam !! 🙏🏽🙏🏽🙏🏽🙌🏻🙌🏻
pravin naga learning this in a university? I can how shitty your university is lmao
@@hanul4989 so what I am also learning this University's second year 3rd semester.
Good for you
I'm doing it in 2nd sem B.Sc
@@thehaseeb9136 same bro
Mam app bht acha padhati ho
Apse ye bolna tha aap sad kyu rhtu ho pls mam aap smile Kiya kro
Or apki smile se hme v himmat milegi study m
My sem exam is Today Afternoon, Now i am watching This concept 😢😂😂
Mam,, I think you have done a mistake..the output Q1 goes to the 2nd flipflop..Not the Q1 bar..because it is up counter..Am I right??please reply...
Yes!
Thank you so much ma'am for such a helpful video 😊
Please make a video on timing diagram for these counters
Thank you Ma'am
I am watching this before 1 hour of exam
We need to take screen shot the notes so please move aside saying time to take screenshots it would be helpfull to remeber from pictures
Bro try here 13:28
madam thank you so much , i have been watching your tutorial both digital and control systems, they are very clear and educative, you the best from Kenya
47746cccv4555
Is she is from kenya
Thank you ma'am
Great explanation
For better experience watch it on 1.5X speed
Are ripple and asynchronous counter same?
Thank you so muchh😭
I RESPECT U MAM U R GREAT KEEP GOING ON❤️
I think for 2 bit ripple up counter to second flipflop we get clk by Q1. Because it is up counter
Both is same doesn't matter whether it is from q1 or q2
Yep she made a mistake
For up counter,If connected from q then clk should have bubble ie +- or q bar connected to clk ie -+ both valid I guess
Mam I think that for up counter u should consider clock of 2nd flip flop from Qa and not Qa^- as it now become down counter.
Well done....++
for positive edge trigger clock is taken from qa' . for negative edge trigger qa is taken as clock
thanks mam
Thanks a lot maam!
madam please practical connection of n modulo counter performance please display on you tube I request you
explain same for 3 bit ripple counter, because if i apply the logic what you are telling it will not work
if you apply correct logic anything would work
Yes bro
Awesome 👍👍👍
Plz explain same for 3 bit also with both positive and negative edge trigger
Thank you so much Mam for your valuable guidance !!! Will you please tell that is 2 bit ripple up counter called as
Mod 4 async counter ? And why ?
@Aravind Badrinathan Thank You So much Sir !
Mam. Can we give the op of Q1 to as clock ip to the next flipflop. If we give the op of complement of Q1 as clock ip then wt is the difference between this two can u say mam plz
Thanks a trillion
Mam can you please give us some written notes about logic families
Nice explanation but you should connect Q1 as 2nd flip-flop clock pulse not (Q1)^ .Now it became a down counter
🤣🤣👍👍👍
Thanks man for teaching us in easy way
mam I have doubt that you have thought the counters reverse.
means up for down counter and down for up counter
Can we take the output from Q1as a clock pulse for 2nd flipflop..?
yes
The principle is for flip flop 1 u need external clock pulse , and for flip flop 2 it takes the output of flip flop 1 as clock pulse ,
This type of counter is known asynchronous counter !!
Can we give the out put of Q1 as clock ip to the next flip flop and why should we give the complement of Q1 as ip to the next flipflop can u say the difference between this two?
Mm negative edge triggered
Always hours away
Well explained....
Thank You Mam !! Nice Explanation!!
mam its a 2bit ripple down counter
you made a mistake
الله يحفضج نقذتيني
Total 4 counts right? Why it is showing 3?
U made a mistake ....check it once....
This is positive triggered edge.
I can understand your concert in simply
Who thought that is crypto ...ripple xrp😂😂
ur teaching is simly marvellous
How easily you descibe it mam😁
Thank you. I understand now.
For the most part.
May be the best....
thankyou mam
Perfect thanks
Why we will consider toogle condition for counters?
If not use the toggle the second output will not come after the first output there is no change if not use the toggle flip flop
mam you teach well but mam please introduce your self
Awesome lesson...
Tooto otto Tu tattatta ayamma.
From Madagascar thankbu
Tq
40
Please explain down counter in mod 12
Excellent !
Thank You ma'm.
Nice lecture
❤️
What is LSB AND MSB
Least significant bit and most significant bit
@@shruthijeevanandam3379 suppose 4 bit counter are there ??howwe take msb and lsb
@@shruthijeevanandam3379 hi
@@sasireddy2544 left most flip flop output is always lsb and the right most flip flop output is msb
D AND SR FF POSSIBLE RIPPLE COUNTERS
I don't think it is possible with them as they do not have a toggle condition.
You have the most brown-est accent.. its so disturbing
Mam can you teach in Hindi