I'm not surprised because two hardware heroes come together, and the outcome is delightful as ever. a lot of details were learned and caught a good idea to observe PL logic using gpio IP on runtime. Thank you, Robert and Adam, keep up good work.
I was thinking the same thing, I get errors from fairly simple RTL modules. But to be fair, he said he did a dry run the day prior. I would expect anyone with this opportunity so qualified would do exactly that.
Thanks very much for this very informative video. I have Arty A7-100T, this guide is largely identical. One major point is that in order to use SSTL135 it needs to move the (pin) bank. But that means the FPGA pin is not the pin for sw_in_0[2] since that is specifically connected (via PCB layout) to FPGA pin C10 (on A7-100T). Now when I generate bitstream with it setup to the default of LVCMOS33 I do not get an error (your video indicated I would if there was a problem). When I inspect the block diagram I see that this is electrically connected to led_fsm_0 and ila_0 and axi_gpio_0. All these block design artefact's are FPGA implemented components. The only thing that appears to connect to ddr3_sdram (which is the part creating a cause of the voltage concerns) is the Memory Interface Generator which is provided and configured by Xilinx wizards with no custom modification to that area of the design afterwards. Then I run the board and C language program from Vitis IDE (part of Vivado 2021.2) and it just works. So I am a little confused what the difference might be with the Arty S7 Spartan-7 board because my block diagram should be the same as yours. I just looked at the Arty-S7-25-Master.xdc and compared to Arty-A7-100-Master.xdc and it does indeed look to be an electrical signal matter specific to the S7 PCB layout (that I can only assume was improved with in the A7 design, these files are at github.com/Digilent/digilent-xdc/ Okay one last point the clock speed of the A7 can run slightly faster so that was a difference I noted. The final working design has sys_clock=100MHz, MIG=200MHz and MicroBlaze=83.333MHz now because of this it maybe necessary just before you perform the final generate bitstream to go back and inspect the axi_uartlite_0 settings, IP Configuration -> AXI CLK Frequency as my initial version the async serial was not working properly (corrupted info displayed). To correct this I change the "AXI CLK Frequency" to "manual" then back to "auto" and the wizard chose a new value. I assume this is a hardware clock divisor based on parameters (such as MicroBlaze clock speed) that is then fixed in FPGA implementation logic. With this change a project respin and the serial was working. Thanks again for your video.
Hi I am also using the same board. Apparently, I am also using the LVCMOS33 for that pin. But the problem is that I am getting errors. Did you follow the exact guideline by adam? Also I could not understand what you did there in clock configuration
Amazing! As a recent grad entering the embedded software world this video is simply amazing. Would love to take a deep dive into the book! Thank Adam for sharing your knowledge and Robert for organising this!
Excellent video ! The only mildly misleading nitpick is that Xilinx has Microblaze MCS core along with Microblaze and MCS is the microcontroller while plain MB they consider a full on CPU. MCS could use more love, imho
Thank you Adam Taylor and @RobertFeranec for the nice video. Just a quick question, what is the name of the VSCODE extension that we should install to be able seeing the Module documentation that Adam should in minute 39:44 of the video?
Great video. There is also opensource alternative - project LiteX. It was not much trouble to run a RiscV with ethernet and DDR3 even for me (minimal fpga skills).
This is great, becuase both Xilinx and Intel have priced their software tools, DDR IP, and VHDL-200x support, beyond the financial reach of the individual, despite the fact that the ONLY use for their software is to enable people to design their chips into products which they then massively profit from. The first FPGA manufacturer to give engineers free software tools will eat all their competitors, becuase every new engineer will learn using their FPGAs, and will then want to keep using that brand when they work for a bigger company.
Great video! I knew what HLS was conceptually but am now less intimidated at trying to create a basic design from scratch. Glad you hosted Adam Taylor and asked some good questions to clarify.
Fantastic video. Thank you to both Adam and Robert. I will be studying the details this project along with the video for some time - not to mention other videos of both you and Adam. Will look forward to other videos as the future unrolls.
Great Tutorial! This video has opened doors for me to explore how FPGAs work, research the difference between ARM technologies and FPGA technology, as well as give me an idea of how many microcontrollers I can fit on one FPGA chip.
Nice to see you two on the same video! Robert, it would be also nice if you switch sides in another session on 1.5 hour dive into high-speed PCB design.
Thank you for this! I can't tell you how awesome your content is. Kudos to you and the guest presenter. I'd be very interested in the Altium book that was mentioned at the end of the podcast. Cheers!
Very interesting and useful video. What would be the procedure to have the code on the board instead of providing it through USB ? Is there an SD card or some flash memory available ?
With a MicroBlaze there are a few options if the program is small enough you can merge the ELF to the block ram and the program will execute on the FPGA is programmed. If you want to use DDR you need to use the merge to merge a boot loader that can cross load from NVRAM to DDR RAM. Xilinx do provide support for that as well so it is pretty straight forward.
Awesome video, I tried to add a microblaze to a demo board ages ago and it all just fell to bits. you have inspired me to have another go. i suspect the tools have come along way since i last attempted it.
Thank you so much for this tutotial! I made more prgress in these 90 minutes than in all the hours I spent on the official stuff! 1:29:11 COM32 - This is one thing I hate about windows. It's USB enumeration is stuck in the 1990's
now i am trying to learn vivado and it is interesting sometimes it hurts but i will do it. It's only a matter of time. very little information is available.
Would love to hear an overview how you constrain the design for timing. Not much was mentioned about it here, but I understand it's one of the more difficult aspects.. and that of writing the proper testbenches!
Very Nice Robert. How hard is it to route DDR3 and DDR4 memory with Altium? Is Metro Graphics a better software fit than Altium? I have a client that wants to run a 28 Gbit project, with many PCB layers and matching impedance possibly 50 ohms on the DDR memory. Possible a fast ethernet fiber application... Any ideas or courses or notes? Rise time and Vias layout. By Pass capacitors, many of them ... Switching regulators.
Thanks for that great video! I pretty sure that many of us would find interesting designing a custom board completely from scratch in Altium Designer exactly for that project instead of using a factory evaluation board. Maybe you should made a video of that stuff in the near future....
It is the same for the Basys3 - just select the basys3 in place of the s7-50 - there is no DDR on the basys3 though you can use the BRAM in place of it and recreate what we had easily. There is a workshop on my site about building pong with the Basys3
Interesting video! FPGAs are really great for those interesting in retro-computing or learning how a CPU works. I am implementing Ben Eater's 8-bit computer in an FPGA in a series of videos on my channel for anyone interested.
Robert, I just watched your old video about Xilinx sending a lawyer after a youtuber. What made you change your mind to again produce content on Xilinx devices?
I wish I could read the text and diagrams (to blurred) - the audio was difficult to understand, also. Frustrating, because I'm sure the content was very interesting.
It would be helpful to cover (or at least point to) why you would want to use an FPGA instead of a cheaper chip. As best I can tell, the answer is either when you have a very parallel problem (so you can use thousands of logic cells instead of just a few cores), or when you have such tight timing constraints that you need to move some processing from software to hardware, but won't need enough units to justify an ASIC. Am I missing something?
I can see your point, of course in reality the Micro is used in commercial FPGA applications for the serial processing - we would deploy the rest of the FPGA the parallel processing systems e.g image processing, signal, filtering or very deterministic control. You will find many micro's in FPGA to do the things which are best performed by a processor, being an engineer is abut picking the right tool for the job. Of course if all you need is a micro then it is overkill.
DON'T USE SOFTCORE MICROCONTROLLERS INSIDE AN FPGA. Use hard cores, multi-cores, SoC, or external interconnections of MCU+FPGA (or these days MPU+MCU+FPGA). Why? Simply because dedicated MCUs are better at doing MCU-like things and dedicated FPGAs are better at doing FPGA-like things (e.g. state machines and SERDES).
It all depends on the application and needs. For some applications ARM core are over kill. But you are right for high performance you really need to use the SoC
Wouldn't you consider to break your videos into several parts? I can only speak by myself, but if I see a video that is one hour and a half I won't even start viewing it. On the other hand, if it is 10 to 15 minutes I will probably check it and, even if it has five more parts I may see them all, perhaps in several days.
The quality of this channel doesn't drop! These are very interesting topics you keep bringing on! Congrats!
Thank you very much Bernardo
@@RobertFeranec hey man I am looking to become a PCB designer and I was wondering if you could answer a few questions for me?
@@mitchelllague5499 please, to ask questions, the best is to use our forum here: designhelp.fedevel.com/
I'm not surprised because two hardware heroes come together, and the outcome is delightful as ever.
a lot of details were learned and caught a good idea to observe PL logic using gpio IP on runtime.
Thank you, Robert and Adam, keep up good work.
Adam Taylor is amazing, to do all that and not get an error is not easy
I was thinking the same thing, I get errors from fairly simple RTL modules. But to be fair, he said he did a dry run the day prior. I would expect anyone with this opportunity so qualified would do exactly that.
I don't have time to fully watch the video but the spots I've seen so far are awesome!
Thanks guys, great video! I just purchased Adam's book as a thank you!! (and to encourage Adam to do more videos!) :)
Thanks very much for this very informative video.
I have Arty A7-100T, this guide is largely identical. One major point is that in order to use SSTL135 it needs to move the (pin) bank. But that means the FPGA pin is not the pin for sw_in_0[2] since that is specifically connected (via PCB layout) to FPGA pin C10 (on A7-100T). Now when I generate bitstream with it setup to the default of LVCMOS33 I do not get an error (your video indicated I would if there was a problem). When I inspect the block diagram I see that this is electrically connected to led_fsm_0 and ila_0 and axi_gpio_0. All these block design artefact's are FPGA implemented components. The only thing that appears to connect to ddr3_sdram (which is the part creating a cause of the voltage concerns) is the Memory Interface Generator which is provided and configured by Xilinx wizards with no custom modification to that area of the design afterwards.
Then I run the board and C language program from Vitis IDE (part of Vivado 2021.2) and it just works.
So I am a little confused what the difference might be with the Arty S7 Spartan-7 board because my block diagram should be the same as yours.
I just looked at the Arty-S7-25-Master.xdc and compared to Arty-A7-100-Master.xdc and it does indeed look to be an electrical signal matter specific to the S7 PCB layout (that I can only assume was improved with in the A7 design, these files are at github.com/Digilent/digilent-xdc/
Okay one last point the clock speed of the A7 can run slightly faster so that was a difference I noted. The final working design has sys_clock=100MHz, MIG=200MHz and MicroBlaze=83.333MHz now because of this it maybe necessary just before you perform the final generate bitstream to go back and inspect the axi_uartlite_0 settings, IP Configuration -> AXI CLK Frequency as my initial version the async serial was not working properly (corrupted info displayed). To correct this I change the "AXI CLK Frequency" to "manual" then back to "auto" and the wizard chose a new value. I assume this is a hardware clock divisor based on parameters (such as MicroBlaze clock speed) that is then fixed in FPGA implementation logic. With this change a project respin and the serial was working.
Thanks again for your video.
Hi I am also using the same board. Apparently, I am also using the LVCMOS33 for that pin. But the problem is that I am getting errors. Did you follow the exact guideline by adam? Also I could not understand what you did there in clock configuration
is the best fpga understand after many years just because this two hours! this two hours is covering pass few years ....
Amazing! As a recent grad entering the embedded software world this video is simply amazing. Would love to take a deep dive into the book! Thank Adam for sharing your knowledge and Robert for organising this!
Excellent video ! The only mildly misleading nitpick is that Xilinx has Microblaze MCS core along with Microblaze and MCS is the microcontroller while plain MB they consider a full on CPU.
MCS could use more love, imho
Your videos are very helpful every day on my job, nice work!!!
Thank you Adam Taylor and @RobertFeranec for the nice video. Just a quick question, what is the name of the VSCODE extension that we should install to be able seeing the Module documentation that Adam should in minute 39:44 of the video?
Thanks From Brasil 🇧🇷 Robert. Great job 👏🏻 👏🏻👏🏻
Pleasure to watch. Adam is a FPGA legend! Thank you for the video Robert.
the TerosHDL editor is amazingly useful. thanks
Great video. There is also opensource alternative - project LiteX. It was not much trouble to run a RiscV with ethernet and DDR3 even for me (minimal fpga skills).
Hello ... I need some help regarding this ...
This is great, becuase both Xilinx and Intel have priced their software tools, DDR IP, and VHDL-200x support, beyond the financial reach of the individual, despite the fact that the ONLY use for their software is to enable people to design their chips into products which they then massively profit from.
The first FPGA manufacturer to give engineers free software tools will eat all their competitors, becuase every new engineer will learn using their FPGAs, and will then want to keep using that brand when they work for a bigger company.
Great video! I knew what HLS was conceptually but am now less intimidated at trying to create a basic design from scratch. Glad you hosted Adam Taylor and asked some good questions to clarify.
The content on this page is second to none. Thank you!
Wow! Definitely mind blowing live demo. It is quite interesting to see how fpgas work in almost 1 hour record.
I did plan to get into FPGA programming for a long time. That tutorial seems simple enough to get started.
Fantastic video. Thank you to both Adam and Robert. I will be studying the details this project along with the video for some time - not to mention other videos of both you and Adam. Will look forward to other videos as the future unrolls.
Great Tutorial! This video has opened doors for me to explore how FPGAs work, research the difference between ARM technologies and FPGA technology, as well as give me an idea of how many microcontrollers I can fit on one FPGA chip.
Very helpful to see how a professional goes through a complex (for me) design
this channel is awesome, in 2 years: How to build an AI supercomputer core, step by step tutorial ;p
Good topics to cover. I always learn something new watching your videos!
Many thanks, Robert!
It was a very useful tutorial video about embedded system designing. Please continue to make more similar videos..... :) Thanks a lot!
Wow!! loved the tutorial.. especially FPGA using IP was actually new!! and intergrating embedded with FPGA was epic.. loved this tutorial
Thank you so much for sharing this on TH-cam, this is so valuable.
Super interesting video. Been wanting to get back into FPGAs for a while now and this gives me confidence!
Very good one! Liked the "live" new feature, very rare to work first time
Good and practical application of FPGA. Easy explained.
Wow guys, great video, keet it up
Hey, This is what I'm working on rn!
Very great video. At the beginning, i couldnt believe, that you can do all that in one and a half hour 👍
Me too
Thank you for your informative video. It really helped.
Nice to see you two on the same video! Robert, it would be also nice if you switch sides in another session on 1.5 hour dive into high-speed PCB design.
Thank you very much Robert, it's really interesting. Thank you Adam too 🎉More fpga please 😁😁😁
Thank you for this! I can't tell you how awesome your content is. Kudos to you and the guest presenter. I'd be very interested in the Altium book that was mentioned at the end of the podcast. Cheers!
Nice collaboration! Good tutorial
Thanks! waiting for more 🎉🎉
Awesome. I’ve always been curious about how to do this! Thank you 😊
Very helpful video! Definately made me more interested in the FPGA field!
Great video!
As always, great video! This looks like a great project to start learning about fpga and get hands on experience with Vivado!
Can't wait for you to get into how signal timing is tuned when a fpga is used and a pcb doesn't have space to do so.
Thanks for the video. Please do a Fpga programming tutorial for beginners.
Great primer on the topic.
Omg, thank you so much, really thank you.
Great video! I'm downloading the tools....
Thank you for your time and for this great tutorial!
Another great video, Robert! Keep it up :)
Amazing video, finally MicroBlaze and AXI makes some sense!
Cool project!
Lovely video! Will have to try FPGAs some day, currently it's mostly various Cortex-M MPUs that goes into the designs.
Both of you are amazing, thank you so much. #respect.
Very interesting and useful video. What would be the procedure to have the code on the board instead of providing it through USB ? Is there an SD card or some flash memory available ?
With a MicroBlaze there are a few options if the program is small enough you can merge the ELF to the block ram and the program will execute on the FPGA is programmed. If you want to use DDR you need to use the merge to merge a boot loader that can cross load from NVRAM to DDR RAM. Xilinx do provide support for that as well so it is pretty straight forward.
That was excellent!
Really good content - many thanks for sharing this - it reveals a whole world of possibilities.
Really thank you
thx robert & adam
if possible pls make much more such amazing fpga videos 👍
love it 🤗
I died at 1:11:50 !!!, We all were pretty excited it worked, maybe he knows what he's doing! :)
A friend who watched the video said Robert and I giggled like school boys when it worked.
Fantastic! The code is inside a microcontroller which is also a code.
Thanks for this video! So interesting, definitely will try it!
Awesome video, I tried to add a microblaze to a demo board ages ago and it all just fell to bits. you have inspired me to have another go. i suspect the tools have come along way since i last attempted it.
You can even add linux to the FPGA processor :)
So good!
Thank you so much for this tutotial! I made more prgress in these 90 minutes than in all the hours I spent on the official stuff!
1:29:11 COM32 - This is one thing I hate about windows. It's USB enumeration is stuck in the 1990's
now i am trying to learn vivado and it is interesting sometimes it hurts but i will do it. It's only a matter of time. very little information is available.
2 Hardware Heros!!!!!
Hey Adam, Is the book available in India?
Nice Video
Thank You!
Would love to hear an overview how you constrain the design for timing. Not much was mentioned about it here, but I understand it's one of the more difficult aspects.. and that of writing the proper testbenches!
great video :-)
Very Nice Robert. How hard is it to route DDR3 and DDR4 memory with Altium? Is Metro Graphics a better software fit than Altium? I have a client that wants to run a 28 Gbit project, with many PCB layers and matching impedance possibly 50 ohms on the DDR memory. Possible a fast ethernet fiber application... Any ideas or courses or notes? Rise time and Vias layout. By Pass capacitors, many of them ... Switching regulators.
Отличное видео, интересно, есть ли у altera что-то похожее
Can u make a single videos on DDR3 protocol only explaining each pin signal
Thanks for that great video! I pretty sure that many of us would find interesting designing a custom board completely from scratch in Altium Designer exactly for that project instead of using a factory evaluation board. Maybe you should made a video of that stuff in the near future....
great thank you
Would you do a video on guard rings in opamp design ?
Again great video as usual :)
Robert have you think about FPGA+embedded Linux? Would be a great topic.
Now that would be interesting to do, we could do that on a Zynq - Adam
I want to download soft copy of the book, can i?
Thank u very much.
I love your channel can you also do some projects with Basys3? I have a Basys3 board😏
It is the same for the Basys3 - just select the basys3 in place of the s7-50 - there is no DDR on the basys3 though you can use the BRAM in place of it and recreate what we had easily. There is a workshop on my site about building pong with the Basys3
@@AdiuvoEngineeringTraining thanks I am going to give it a go. I hope I can find the right connections 😏
@@AdiuvoEngineeringTraining i would like to get my hands on your give away board🙂
Interesting video! FPGAs are really great for those interesting in retro-computing or learning how a CPU works. I am implementing Ben Eater's 8-bit computer in an FPGA in a series of videos on my channel for anyone interested.
Thank you
How 81mhz is quarter of 200mhz?
My compiler doesn't like "printf" if I want to print my GPIO data... I have to use "xil_printf"
Robert, I just watched your old video about Xilinx sending a lawyer after a youtuber.
What made you change your mind to again produce content on Xilinx devices?
I still do not like Xilinx - I still remember very well what they did. But I do like to learn new things.
What a great video, any chance of more?
Maybe a walkthru like this but using Xilinx ZYNQ FPGA to get Linux running on a 7010?
I wish I could read the text and diagrams (to blurred) - the audio was difficult to understand, also. Frustrating, because I'm sure the content was very interesting.
WOW
It would be helpful to cover (or at least point to) why you would want to use an FPGA instead of a cheaper chip. As best I can tell, the answer is either when you have a very parallel problem (so you can use thousands of logic cells instead of just a few cores), or when you have such tight timing constraints that you need to move some processing from software to hardware, but won't need enough units to justify an ASIC. Am I missing something?
Did you try building it yet Robert ? Adam
Adam, not yet. I have couple of ideas how I could make a video about following this tutorial. The board is ready on my table.
🌷 Promo-SM!!!
Its all right, but where Xilinx FPGA IC on digikey or mouser? 52 weeks for production is very badly joke
I thought i read "microtransaction in FPGA"😂
MCU
$500 microcontroller lets do it !
I can see your point, of course in reality the Micro is used in commercial FPGA applications for the serial processing - we would deploy the rest of the FPGA the parallel processing systems e.g image processing, signal, filtering or very deterministic control. You will find many micro's in FPGA to do the things which are best performed by a processor, being an engineer is abut picking the right tool for the job. Of course if all you need is a micro then it is overkill.
$10 FPGAs are already big enough to host quite capable soft cores
DON'T USE SOFTCORE MICROCONTROLLERS INSIDE AN FPGA. Use hard cores, multi-cores, SoC, or external interconnections of MCU+FPGA (or these days MPU+MCU+FPGA). Why? Simply because dedicated MCUs are better at doing MCU-like things and dedicated FPGAs are better at doing FPGA-like things (e.g. state machines and SERDES).
It all depends on the application and needs. For some applications ARM core are over kill. But you are right for high performance you really need to use the SoC
Wouldn't you consider to break your videos into several parts?
I can only speak by myself, but if I see a video that is one hour and a half I won't even start viewing it. On the other hand, if it is 10 to 15 minutes I will probably check it and, even if it has five more parts I may see them all, perhaps in several days.