After doing a couple of hour of observation and trying different combination of gates for flip-flop I came up with these conclusions. Things get really confusing when we moved to the J-K flip flop. Let’s start from beginning, We’ve two data storing elements i.e. 1: SR NOR Latch 2: SR NAND Latch They work the same but their truth tables are completely opposite to each other. i.e. SR NOR Latch truth table S R Q 0 0 Memory state 1 0 1 0 1 0 1 1 Not used SR NAND Latch truth table S R Q 0 0 Not used 1 0 0 0 1 1 1 1 Memory state After studying these basic memory elements. We moved to SR latches with “enable”. This enable is input to the two NAND gates along with Set and Reset (as in the circuit diagram shown in video). The output of these two NAND gates is input to the Latch (SR NAND). If we replace “enable” by “Clock” we would have a flip flop. Let me ask you a question. Can’t we use any other combination of gates? Of course, we can. See the possible combinations which will work as an SR flip flop. 1. AND-NOR 2. NOR-NOR 3. OR-NAND 4. NAND-NAND (Used in video) You must be thinking what about the other combinations? 5. NAND-NOR 6. OR-NOR 7. AND-NAND 8. NOR-NAND These combinations (5 to 8) will not work as flip flop. Try making truth table for each of these combinations. After making truth table, You’ll realise that these circuits (5 to 8) are automatically going into “Invalid State” when the clock is Low/High depending upon the circuit configuration. Flip flop must follow one property, if clock goes Low or High, it must have a memory state. See these circuits are not storing data we can’t use these combinations. The only possible combinations which will work as an SR flip flop are: 1. AND-NOR 2. NOR-NOR 3. OR-NAND 4. NAND-NAND (Used in video) Hope, it cleared your doubt till now. But as we move to J-K and T flip flop. We again have some limitations. We get J-K flip flop when we feedback Q’ to the top NAND gate and Q to the bottom NAND gate Using this type of arrangement of feedback. Only two possible combinations will work i.e. 1. NOR-NOR 2. NAND-NAND Did you see? We started with 8 combinations and end up having only two useful combinations for J-K and T flip flop. If you want to use the remaining combinations for J-K and T flip flop 1. AND NOR 2. OR NAND Then, these two combinations can also be used if we make some changes in the feedback arrangement. Suppose, if we have an AND-NOR SR flip flop we want to make JK flip flop then we have to use this configuration, “If Q is input to the top AND gate and Q’ is input to the bottom AND, using this configuration the remaining two (AND-NOR, OR-NAND) will also work.” I tried every possible combination and their truth table. Everything in this video is correct and accurate. Hope it helped you!
your stuff is kinda wrong in terms how it is tought in my school. Here truth tables are the same with any gates, what changes are the inputs and the scheme IE in SR latch with nand if you give top input s and bottom input r while top output is q then you will get the opposite of regular truth table however in my university that is considered a nonsensical trigger. You have to give both inputs reversed, so top input is 'not s' bottom is 'not r' ;;;; outputs: top 'q' bottom 'not q' though there are other combination where the table would be correct as well IE nR->nQ nS->Q and only difference of sr and jk is the 11 in sr is undefined and in jk is reversed.
@@last_time_I_pooped_was I'm a working electrical engineer and pursuing my PhD. As an added note, I've never mentioned, used, or required knowledge about JK flip-flops since the computer engineering course at the time of the above comment. Everything is based on the D flip-flop.
I had digital electronics paper today..al I did ystrdy was watching ur videos.and im nw here typing my gratitude. thank you so much brother...you have brought satisfaction in me.cos I really feel having learned something.
I have tried to understand JK flipflips for 15 years now and FINALLY I understand what they are, An SR latch with an extra feature ! TOGGLE. My goodness, THANK YOU !!
00:06 JK flip-flop provides an advantage over SR and D flip-flops. 00:51 Introduction to JK flip-flop 01:42 The JK flip-flop has two outputs Q and Q complement. 02:50 JK flip-flop and SR flip-flop have similar outputs except for the last case. 04:06 Analyzing the values for Q and Q complement 05:03 NAND SR latch can produce different outputs based on input changes 06:01 The JK flip-flop races between 0 and 1 06:58 JK flip flop output is the complement of the previous state.
for anyone having trouble remembering this, i suggest you think of it like this: Only when Q = 1, the device can be Reset, and only when Qn = 1, the device can be set. Just as a tip for remembering it more easily 😊
i also got confused but now figured it. The TT is for SR-FF : for this remember that SR FF consists of a SR Latch. Here the inputs are S,R for the FF, but the inputs of the embedded SR Latch are S* , R*. So if you consider the TT with the inputs as S*, R* then the Qn+1 values satisfies the SR NAND latch TT.
Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share Go from (Qn+1)' output (Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1 Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate Q' = 0, ( Qn+1 )' = 1 (Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0 so Now states become, OLD -> Qn' = 0 NEW -> (Qn+1)' = 1 OLD -> Qn = 1 NEW -> (Qn+1) = 0 Now you can use this as a new input for the next cycle, to toggle again its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse Fucking wasted my hours zzzz
In 5:13 you said that the when input is 0, 1 from clock and 1 from K, then nand output is 1 but it should be zero, right!? And gate for three inputs 0 1 1 the output should be 1 and the compliment of it should be zero, correct me if I am wrong!
That was a wonderful presentation! However, I do wanna point out that there are two main variations on the SR Latch (which are used to synthesize the JK Flip Flop)...refer to the previous video as self-evidence. WHY DOES THAT MATTER? ==>> The NOR type preserves the memory state of Q, Q_bar whenever S = R = ‘0’; S = R = ‘1’ results in the forbidden state. The NAND gate simply inverts the relationship, where all ‘0’ is forbidden and all ‘1’ is the memory preservation state. I noticed that the SR schematic is NAND based, whereas its truth table is NOR based...an alleged contradiction, if you will. I’m not a seasoned pro at this, but I think my observation makes sense, and can be used to improve the insight that you provided. Again, great video, (& to the viewers, take the presentation with a grain of salt). :) I’ll keep watching, Neso Academy. Have a great day!
Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share Go from (Qn+1)' output (Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1 Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate Q' = 0, ( Qn+1 )' = 1 (Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0 so Now states become, OLD -> Qn' = 0 NEW -> (Qn+1)' = 1 OLD -> Qn = 1 NEW -> (Qn+1) = 0 Now you can use this as a new input for the next cycle, to toggle again its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse Fucking wasted my hours zzzz
Here,T.T. for SR f/f using NOR gate and and the diagram for RS f/f using NAND gate, which is quite overwhelming if you are looking table and the diagram parallely , so nerds don't get confused 😕
Sir, I am very thankful to you for this.aapke lectures se Maine bahut ache marks obtained kiye.warna meri reappear thi sir electronic mein.thanks sir......
"you have already studied about the SR flip-flop and D flip-flop so what is the need to study the next type of flip-flop that is your third flip-flop" YES EXACTLY WHAT I'M THINKING, WHYYYY
Hi NESO, If Q is given back to J NAND gate Q' is given back to K NAND gate,Also toggiling occurs. You proved that you are good teacher.And you has a knowledge sharing great habit.🙋🏻♂️
If I assume Qn-1 = 1 and ~Qn-1 = 0, and I also set c=1, j=1 and k = 0, then the Inputs of the last nand gates (so the one for the latch) are both 0 and 1, which would result in Qn =1 and ~Qn = 1 if you go and check the network (not the truth table).
Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share Go from (Qn+1)' output (Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1 Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate Q' = 0, ( Qn+1 )' = 1 (Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0 so Now states become, OLD -> Qn' = 0 NEW -> (Qn+1)' = 1 OLD -> Qn = 1 NEW -> (Qn+1) = 0 Now you can use this as a new input for the next cycle, to toggle again its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse Fucking wasted my hours zzzz
thank you so much for putting this much efforts and making it very clear and I'm really hoping that you are going to upload the the sequential circuits designing and analysis and the state digram because I have exam this week and can't find any good resources
Man, you are awesome. I'm studying for my test and you are the only guy that I understand! thank you so much for helping me. I'll drop my PayPal contribution on your website tomorrow. keep the great work!
David Stern well ur doubt is correct but actually the mistake u r doing is that u r taking both the feedback values simultaneously dont do it simultaneously first take one feedback at a time and let the value of the one output change then take that changed new value as the feedback value for the other nand gate.You will get the correct answer.but here also start from the upper flip flop and not from the lower flip flop take the feedback that upper flip flop is getting get the new output and then take it as a feedback to lower flipflop. the reason for this is that nomatter how similar two flip flops are they always has some speed difference in them which is of the order of picoseconds so we have assumed here by taking q=0 and !q=1 that the upper flip flop is faster so it will get the feedback first.....hope ur doubt is cleared now
In 3:15 I don't get why the TT for JK and SR FFs are the same. E.g. if J=1 and K=0, the output of the K-NAND equals 1 because K=0, but what would prevent the output of J-NAND from also being 1 and the latch being in memory state if neg(Q) was 0 previously ?
In J-k flip flop you have made use of 3 input NAND gate with 1.J 2.clk and 3 .k Until and unless we get all.3 input how will the gate work or there is previous some Q and Q bar going in 3 input NAND gate , please clarify it
the value of Q will depend on the previous state before input becomes 1,1 . so the Q value doesnt matter, it could be 0 or 1 but the working will be same
5:20 you say when input of sr ff is 0 and 1 the output is 1 and 0. but it's wrong. according to the table when input is 0 and 1 output is 0 and 1 only. o.O help
U don't but if u see the nand truth table when ever one input is 0 then irrespective of 2 input we can say the output will always be 1.so if J=0 and K=1(0,1) input we take the Q=1 and then we pass this 1 as 2nd input of k and thus ~Q =0. Hope this help
NESCO ACADEMY THERE IS A MISTAKE AT 3:00 when the case is j=1,k=0 you just assumed j=S and k=R saying that the truth table is same for JK and SR , you didn't derive JK truth table and proved it is same.
hello there . i do have a very simple questions at 5:30 you said when we have 0 and 1 in SR latch the result actually is that Q =0 and not to 1 based on the table you have on your presentation any answer would be helpful .
He was actually replying to some other person's comments. But it seems like that other person has deleted his comments and this conversation looks one sided.
Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share Go from (Qn+1)' output (Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1 Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate Q' = 0, ( Qn+1 )' = 1 (Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0 so Now states become, OLD -> Qn' = 0 NEW -> (Qn+1)' = 1 OLD -> Qn = 1 NEW -> (Qn+1) = 0 Now you can use this as a new input for the next cycle, to toggle again its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse Fucking wasted my hours zzzz
So what do the JK, D, SR and T flip flops do in general? Do they control the amount of duty cycles in a wave, change the waveform, etc... ? I am still a little confused.
sir in the sequential circuits playlist, you haven't added video of characteristic and excitation table of d flip flop.You directly moved onto JK flip flop. Please add it to the playlist too.
I don't know why you have choosen as Q and Q complement different in last case... What does the meaning of last state if you taken as Different ? I don't know why... But I think there should be some different explanation to it....
In the last case where clk=J=k=1, why do we assume Q=0 and Q'=1? In the very first instance, shouldn't both Q & Q' are zero when we try to get to the State Q1?
You guys are confusing the basic SR latch truth table, with the full SR flip flop truth table (which has two extra NAND gates)... S* and R* were shown in the truth table you are confused by. The addition of the two NANDs at the left side means S* and R* are inverted relative to what you saw before. So it makes it clearer actually, as S means set finally and R means reset, for values of 1.
you took j=0 k=1 as similar to sr flipflop can you explain it on jk directly how it is coming that output ...without taking reference of sr flip flop..
I have a question. Initially you had shown a S- R Flip Flop with S and R as two inputs with clock pulse present. That indicates that the NAND gates present in the first level are two input NAND gates. If this is the case then how a third input (Q or it's complement) can be added as one more input to these NAND gates? In this process the two input gates are changing to 3 input gates.
but your explanation is under "assume" n 4:16 , but what is the reality ? and the result Qn+1for (clk, S, R) (1,1,1) is Qn' , if they are racing why Qn' ?? and how become toggle ? as in "assume" condition ?? assume is not real right ??
@mas bro Because no matter what assume at the beginning for Q and Q(not), the result is always a toggle - a change of state. Therefore, you will have constant switch b/n 0 and 1. It's all about change of the state.
+Rahul Vashist As in the truth table of SR flip flop using NAND gates the contradiction occurs when S and R both are 0. Not 1. As you have explained in your earlier vidoes.
Hi, thanks for the video. I have a question. Why is the truth table for an SR NOR gate flip flop when the SR flip flop in the diagram is a NAND type? Thank you.
I noticed he mistakenly put truth table for the SR latch using NOR gates, but in the video he used SR latch using NAND gate. If u watch the video about the SR latch, u will noticed his mistake.
You should correct this video, it is confusing. If your talking about RS FF the memory state is "00" and "11" is forbidden state. The memory condition in SR FF is "11" and "00" is the not used one. Thanks
Hi Neso Academy, your videos are really help full, thanks for the easy explanations. for the JK flip flop i have a question, why are we considering the output of clk, S and R as Q(n+1) and why not just Q? this is causing a lot of confusion since the value iof Q and Q(n+1) are opposites. please help !!
sir I think there is a mistake. during the second round you have 1 at the input of upper right nand gate and 0 through Qbar. so the output should be 1and not 0. please explain. thank you
5:20, You said for SR(0,1) output is (Q = 1, Q' = 0) for NAND SR. Then in SR FF video, you said that when SR FF is implemented using NAND gate then, (0, 0 ) is 'not used' condition. But here, you are saying that 1,1 is not used condition even though its NAND gate. SR NAND Latch truth table S R Q 0 0 Not used 1 0 0 0 1 1 1 1 Memory state Can you please explain how and why ?
Esne confuse kr diya hai aapko dusra video dekhna pdega.. Truth table nor ka hai example ckt nand ka.. Ckt desigh bhi RS ki jaga SR ka h.. Avoid this video!
After doing a couple of hour of observation and trying different combination of gates for flip-flop I came up with these conclusions.
Things get really confusing when we moved to the J-K flip flop.
Let’s start from beginning,
We’ve two data storing elements i.e.
1: SR NOR Latch
2: SR NAND Latch
They work the same but their truth tables are completely opposite to each other. i.e.
SR NOR Latch truth table
S R Q
0 0 Memory state
1 0 1
0 1 0
1 1 Not used
SR NAND Latch truth table
S R Q
0 0 Not used
1 0 0
0 1 1
1 1 Memory state
After studying these basic memory elements. We moved to SR latches with “enable”. This enable is input to the two NAND gates along with Set and Reset (as in the circuit diagram shown in video). The output of these two NAND gates is input to the Latch (SR NAND). If we replace “enable” by “Clock” we would have a flip flop.
Let me ask you a question. Can’t we use any other combination of gates?
Of course, we can.
See the possible combinations which will work as an SR flip flop.
1. AND-NOR
2. NOR-NOR
3. OR-NAND
4. NAND-NAND (Used in video)
You must be thinking what about the other combinations?
5. NAND-NOR
6. OR-NOR
7. AND-NAND
8. NOR-NAND
These combinations (5 to 8) will not work as flip flop. Try making truth table for each of these combinations. After making truth table, You’ll realise that these circuits (5 to 8) are automatically going into “Invalid State” when the clock is Low/High depending upon the circuit configuration. Flip flop must follow one property, if clock goes Low or High, it must have a memory state. See these circuits
are not storing data we can’t use these combinations.
The only possible combinations which will work as an SR flip flop are:
1. AND-NOR
2. NOR-NOR
3. OR-NAND
4. NAND-NAND (Used in video)
Hope, it cleared your doubt till now.
But as we move to J-K and T flip flop. We again have some limitations.
We get J-K flip flop when we feedback Q’ to the top NAND gate and Q to the bottom NAND gate
Using this type of arrangement of feedback. Only two possible combinations will work i.e.
1. NOR-NOR
2. NAND-NAND
Did you see? We started with 8 combinations and end up having only two useful combinations for J-K and T flip flop.
If you want to use the remaining combinations for J-K and T flip flop
1. AND NOR
2. OR NAND
Then, these two combinations can also be used if we make some changes in the feedback arrangement.
Suppose, if we have an AND-NOR SR flip flop we want to make JK flip flop then we have to use this configuration,
“If Q is input to the top AND gate and Q’ is input to the bottom AND, using this configuration the remaining two (AND-NOR, OR-NAND) will also work.”
I tried every possible combination and their truth table. Everything in this video is correct and accurate.
Hope it helped you!
your stuff is kinda wrong in terms how it is tought in my school. Here truth tables are the same with any gates, what changes are the inputs and the scheme
IE in SR latch with nand if you give top input s and bottom input r while top output is q
then you will get the opposite of regular truth table however in my university that is considered a nonsensical trigger. You have to give both inputs reversed, so top input is 'not s' bottom is 'not r' ;;;; outputs: top 'q' bottom 'not q'
though there are other combination where the table would be correct as well IE
nR->nQ
nS->Q
and only difference of sr and jk is the 11 in sr is undefined and in jk is reversed.
Wow great..... excellent understanding
😨
thanx saved me a lot of time
Bhai logic gates ki sale lagi thi kya
Learned more in 20 minutes of these videos than a full month in my CMP ENG course. Life saver.
Now what are you doing in ur life?
@@last_time_I_pooped_was I'm a working electrical engineer and pursuing my PhD.
As an added note, I've never mentioned, used, or required knowledge about JK flip-flops since the computer engineering course at the time of the above comment. Everything is based on the D flip-flop.
@@last_time_I_pooped_was i was wondering this too
how in the world did you not learn about flip flop circuits
Pretty Dumb I guess
At 2:04 we have the truth table for Sr ff with nor gate but we are using the diagram of Sr with nand gate these two totally gives different outputs
yes same doubt..
that is sr filp flop with NAND gate and that is correct. you are talking about sr latch with nor gate.
I had digital electronics paper today..al I did ystrdy was watching ur videos.and im nw here typing my gratitude. thank you so much brother...you have brought satisfaction in me.cos I really feel having learned something.
I dont understand .why it is getting dislikes..you are getting a great job sir..with a great teaching
because he calls latches flipflops
There are teacher of our college who didn't explain
@Prateek Patel okay. I'll watch .
Dislike are from those teachers who were expelled for not teaching well...
TH-cam removed dislike are you happy now ?
I have tried to understand JK flipflips for 15 years now and FINALLY I understand what they are, An SR latch with an extra feature ! TOGGLE. My goodness, THANK YOU !!
00:06 JK flip-flop provides an advantage over SR and D flip-flops.
00:51 Introduction to JK flip-flop
01:42 The JK flip-flop has two outputs Q and Q complement.
02:50 JK flip-flop and SR flip-flop have similar outputs except for the last case.
04:06 Analyzing the values for Q and Q complement
05:03 NAND SR latch can produce different outputs based on input changes
06:01 The JK flip-flop races between 0 and 1
06:58 JK flip flop output is the complement of the previous state.
EE101
thank you :3
for anyone having trouble remembering this, i suggest you think of it like this: Only when Q = 1, the device can be Reset, and only when Qn = 1, the device can be set. Just as a tip for remembering it more easily 😊
1:00 Why does the logic diagram represents a SR flip-flop with NAND gate but the truth table is of a NOR gate SR flip-flop?
exactly. confused me too.
i also got confused but now figured it.
The TT is for SR-FF : for this remember that SR FF consists of a SR Latch. Here the inputs are S,R for the FF, but the inputs of the embedded SR Latch are S* , R*.
So if you consider the TT with the inputs as S*, R* then the Qn+1 values satisfies the SR NAND latch TT.
Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share
Go from (Qn+1)' output
(Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1
Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate
Q' = 0, ( Qn+1 )' = 1
(Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0
so Now states become,
OLD -> Qn' = 0
NEW -> (Qn+1)' = 1
OLD -> Qn = 1
NEW -> (Qn+1) = 0
Now you can use this as a new input for the next cycle, to toggle again
its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse
Fucking wasted my hours zzzz
Man, i just wanna thank you for your videos, they helped me out in Varsity...i graduated last year but, Thank you so much💪💪❤
u r simply amazing! i hope you get all the success u deserve
In 5:13 you said that the when input is 0, 1 from clock and 1 from K, then nand output is 1 but it should be zero, right!? And gate for three inputs 0 1 1 the output should be 1 and the compliment of it should be zero, correct me if I am wrong!
OK got it, And gate means all input true then Output is true!
That was a wonderful presentation! However, I do wanna point out that there are two main variations on the SR Latch (which are used to synthesize the JK Flip Flop)...refer to the previous video as self-evidence. WHY DOES THAT MATTER? ==>> The NOR type preserves the memory state of Q, Q_bar whenever S = R = ‘0’; S = R = ‘1’ results in the forbidden state. The NAND gate simply inverts the relationship, where all ‘0’ is forbidden and all ‘1’ is the memory preservation state. I noticed that the SR schematic is NAND based, whereas its truth table is NOR based...an alleged contradiction, if you will. I’m not a seasoned pro at this, but I think my observation makes sense, and can be used to improve the insight that you provided. Again, great video, (& to the viewers, take the presentation with a grain of salt). :) I’ll keep watching, Neso Academy. Have a great day!
+Oswald Chisala this is really confusing me how can we use NAND based rs F-F while using NOR based f-f ??
Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share
Go from (Qn+1)' output
(Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1
Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate
Q' = 0, ( Qn+1 )' = 1
(Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0
so Now states become,
OLD -> Qn' = 0
NEW -> (Qn+1)' = 1
OLD -> Qn = 1
NEW -> (Qn+1) = 0
Now you can use this as a new input for the next cycle, to toggle again
its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse
Fucking wasted my hours zzzz
Here,T.T. for SR f/f using NOR gate and and the diagram for RS f/f using NAND gate, which is quite overwhelming if you are looking table and the diagram parallely , so nerds don't get confused 😕
Sir, I am very thankful to you for this.aapke lectures se Maine bahut ache marks obtained kiye.warna meri reappear thi sir electronic mein.thanks sir......
"you have already
studied about the SR flip-flop and D flip-flop so what is the need to study the next type of flip-flop that is your third flip-flop"
YES EXACTLY WHAT I'M THINKING, WHYYYY
Hi NESO,
If Q is given back to J NAND gate
Q' is given back to K NAND gate,Also toggiling occurs. You proved that you are good teacher.And you has a knowledge sharing great habit.🙋🏻♂️
explained....the whole concept in a very simple manner,..... thank u sir.....
Sir you are a legend. I hope you get very successful in your life!
Your lectures are very helpful.
If I assume Qn-1 = 1 and ~Qn-1 = 0, and I also set c=1, j=1 and k = 0, then the Inputs of the last nand gates (so the one for the latch) are both 0 and 1, which would result in Qn =1 and ~Qn = 1 if you go and check the network (not the truth table).
U are correct
Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share
Go from (Qn+1)' output
(Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1
Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate
Q' = 0, ( Qn+1 )' = 1
(Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0
so Now states become,
OLD -> Qn' = 0
NEW -> (Qn+1)' = 1
OLD -> Qn = 1
NEW -> (Qn+1) = 0
Now you can use this as a new input for the next cycle, to toggle again
its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse
Fucking wasted my hours zzzz
Congratulations 👏👏🎊 sir for 1million subscribers , keep growing
Uyyyy7w
thank you so much for putting this much efforts and making it very clear and I'm really hoping that you are going to upload the the sequential circuits designing and analysis and the state digram because I have exam this week and can't find any good resources
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
he wouldve done them if you weren't screaming at him. thanks a lot.
Sir when the CLK is low the circuit will get off by having the previous outputs in memory but why get J* and K* as 1..
At 2:40 in the video
First time i understood toggling. You are legendary man🙏
Man, you are awesome. I'm studying for my test and you are the only guy that I understand!
thank you so much for helping me.
I'll drop my PayPal contribution on your website tomorrow. keep the great work!
at 5:21 both nand gates in the second set are recieving 01 so both their outputs should be 1, no?
David Stern well ur doubt is correct but actually the mistake u r doing is that u r taking both the feedback values simultaneously dont do it simultaneously first take one feedback at a time and let the value of the one output change then take that changed new value as the feedback value for the other nand gate.You will get the correct answer.but here also start from the upper flip flop and not from the lower flip flop take the feedback that upper flip flop is getting get the new output and then take it as a feedback to lower flipflop.
the reason for this is that nomatter how similar two flip flops are they always has some speed difference in them which is of the order of picoseconds so we have assumed here by taking q=0 and !q=1 that the upper flip flop is faster so it will get the feedback first.....hope ur doubt is cleared now
In 3:15 I don't get why the TT for JK and SR FFs are the same. E.g. if J=1 and K=0, the output of the K-NAND equals 1 because K=0, but what would prevent the output of J-NAND from also being 1 and the latch being in memory state if neg(Q) was 0 previously ?
Thank u sir for providing such a nice explanations on the sequential circuits..it is really helpful to Me..
type sht
In J-k flip flop you have made use of 3 input NAND gate with 1.J 2.clk and 3 .k
Until and unless we get all.3 input how will the gate work or there is previous some Q and Q bar going in 3 input NAND gate , please clarify it
@5:27 can someone help me out here
As S=0 R=1 and using SR Latch output must be ie Q=0 but here sir is writing 1
How ??
Kindly help ASAP 🙏
Same
sir how can we assume ourr self the value of Q (4:20)
the value of Q will depend on the previous state before input becomes 1,1 . so the Q value doesnt matter, it could be 0 or 1 but the working will be same
5:20 you say when input of sr ff is 0 and 1 the output is 1 and 0. but it's wrong. according to the table when input is 0 and 1 output is 0 and 1 only. o.O help
i noticed that too .... but its right for nand sr output
NAND gate 😑
kunal choudhary yes dude i got you
he is correct, notice he said "SR LATCH" not "SR ff",
Aman Deep we have to use truth table of latch and not flip flop
+ Neso Academy how did u know what is the value of Q and Q' , accept the last case where u assumed
U don't but if u see the nand truth table when ever one input is 0 then irrespective of 2 input we can say the output will always be 1.so if J=0 and K=1(0,1) input we take the Q=1 and then we pass this 1 as 2nd input of k and thus ~Q =0.
Hope this help
Thankuuuuuu sir
You really help us alot.
Clear concepts in a seconds.
You really make difficult subjects easy.
Thnku so much for making this things so easy for us☺ u were a life saver to me😊
Wow, your presentation was really helpful! Thanks :)
NESCO ACADEMY THERE IS A MISTAKE AT 3:00 when the case is j=1,k=0 you just assumed j=S and k=R saying that the truth table is same for JK and SR , you didn't derive JK truth table and proved it is same.
hello there . i do have a very simple questions at 5:30 you said when we have 0 and 1 in SR latch the result actually is that Q =0 and not to 1 based on the table you have on your presentation any answer would be helpful .
marouane bicher you have to refer to basic SR Latch table . When Reset = 1, Qnot=0
@@munirahmoorman3602 thanks bro
Iam too wasted my time there
Happy teacher's day...Sir. Your videos helps me a lot. Please make video on electromagnetic.
sir ,i have been hearing your voice by this tutorial ,i just i want to see your face ,your tutorials are really awesome
see you are crossing in my way
did i do anything to u
i just like that video whats wrong with that . You said "gay" that was really annoyed me
so sry if i hurt You.plz dont cross my way.
He was actually replying to some other person's comments. But it seems like that other person has deleted his comments and this conversation looks one sided.
Thanks again and again sir for your work
Don't you think so, that clk. Must be edge triggered (as per diagram) ?
5:20 when we gave inputs s=0 and R= 1 for the SR NAND latch the answer should be Q=0 and Q' = 1 but why is Q=1 and Q' =0
It is a NAND SR flipflop which is an active low input, hence the apparent inversion.
becoz thats actually s* and r* that we give to the latch
Bro, I just understood it, took me 2 hours. No one has explained properly zzzz -_-, let me share
Go from (Qn+1)' output
(Qn+1)' = ( ( Q * K * C )' * Q )' = ( (1*1*1)' * 1 )' = ( 1' * 1 )' = ( 0 * 1 )' = 0' = 1
Treat this as an input in (Qn+1) at the end, but use the old Q' at the first Gate
Q' = 0, ( Qn+1 )' = 1
(Qn+1) = ( ( Q' * K * C )' * (Qn+1)' )' = ( ( 0 * 1 * 1 )' * 1 )' = ( 0' * 1 )' = 1' = 0
so Now states become,
OLD -> Qn' = 0
NEW -> (Qn+1)' = 1
OLD -> Qn = 1
NEW -> (Qn+1) = 0
Now you can use this as a new input for the next cycle, to toggle again
its kinda confusing, Also some textbooks don't even consider it as a proper JK Flip Flop, since it doesn't work on single Clock Cycle But Pulse
Fucking wasted my hours zzzz
Is it confusing only for me? :(
Yes
Just discovered these lectures. Now I don't have to worry about my CC V
Thank you so much sir. You are simply marvelous.
Tq sir.this videos are very usefull to me.any one cam understand ur lecturing easily. Way of teaching i loved it thanq sir
So what do the JK, D, SR and T flip flops do in general? Do they control the amount of duty cycles in a wave, change the waveform, etc... ? I am still a little confused.
Have you figured it out because I'm also confused
@@maxbreaker which part are you confused on? I might be able to help
sir in the sequential circuits playlist, you haven't added video of characteristic and excitation table of d flip flop.You directly moved onto JK flip flop. Please add it to the playlist too.
isnt that a truth table for SR in a NOR?
I wish i found this channel sooner. finals are coming up.... gonna watch a few vids to save my grade loool
I understood the concept well thank you so much sir👍
why u are taking inputs at s=1 r=1 and latch at 2:45 sec and saying it as memory state??
Great Explanation, one in a million!
Thank you very much!
His way of teaching makes me feel like... It's an offline class. Mean face to face.
I don't know why you have choosen as Q and Q complement different in last case... What does the meaning of last state if you taken as Different ? I don't know why... But I think there should be some different explanation to it....
In the last case where clk=J=k=1, why do we assume Q=0 and Q'=1? In the very first instance, shouldn't both Q & Q' are zero when we try to get to the State Q1?
the truth table used is related to nor gater SR latch and you draw and explain all the video using the nand gates SR latch !
i also agree with omer..plz explain
he is using the truth table of nand, not that of nor
you are confusing between sr flip flop and latch
You guys are confusing the basic SR latch truth table, with the full SR flip flop truth table (which has two extra NAND gates)... S* and R* were shown in the truth table you are confused by. The addition of the two NANDs at the left side means S* and R* are inverted relative to what you saw before. So it makes it clearer actually, as S means set finally and R means reset, for values of 1.
sir used clocked s R flip flop using nand gata.
it is correct
sir, in 2:57 why you considered that when j= 1 , k=0 is same as SR flip flop ?
you took j=0 k=1 as similar to sr flipflop
can you explain it on jk directly how it is coming that output ...without taking reference of sr flip flop..
Exactlyyyyy !
i need to understand that
😎😎Legends watching this after 6 years 😎😎😎😎
I think i am ultra legend then i am watching it after 9 years
@@Learn_from_Zero24 Lol same here
Is there a difference between a JK flipflop formed from an SR(using nor gates) and other SR(using NAND)?
yes
Explaination method is excellent
Great explaination sir I was totally understanded thank you for sharing this sir♥️👌
To the legend who found this tutorial 20mins before exam
I have a question. Initially you had shown a S- R Flip Flop with S and R as two inputs with clock pulse present. That indicates that the NAND gates present in the first level are two input NAND gates.
If this is the case then how a third input (Q or it's complement) can be added as one more input to these NAND gates? In this process the two input gates are changing to 3 input gates.
yes.. it can be done.. we have a separate IC for three input NAND gate (IC7410)
Isn't the truth table you have for the SRFF for the nor gate implementation?
but your explanation is under "assume" n 4:16 , but what is the reality ? and the result Qn+1for (clk, S, R) (1,1,1) is Qn' , if they are racing why Qn' ?? and how become toggle ? as in "assume" condition ?? assume is not real right ??
@mas bro Because no matter what assume at the beginning for Q and Q(not), the result is always a toggle - a change of state. Therefore, you will have constant switch b/n 0 and 1. It's all about change of the state.
but if we assume like that then what is the need of jk flip flop.what if we have assumed same thing in SR flip flop
J and K inputs should be swapped. When J goes high, we should see Q output high, and in your video it is opposite (wrong)
My que is :
In jk ff when clk is 1 n j=0 k=0 why u hvnt consider qn n it's compliment as third input with j and similarly for k also.
are you trying to tell me, with a JK flipflop and two high inputs, it will flipflop?
Madness!
PS, actually very helpful. Thankyou :)
The truth table is for SR flip flop using NOR gates and the diagram you have made is using NAND gates. Am I right ?
+Rahul Vashist As in the truth table of SR flip flop using NAND gates the contradiction occurs when S and R both are 0. Not 1. As you have explained in your earlier vidoes.
For all those saying the truth table is wrong, its NOT. The truth tables of NOR SR Latch and NAND SR Flip flop are almost similar.
Thanks sir, All your lectures are well explained. Thanks :)
why do we only consider the third input for the situation that J and K are both 1's? what about the situations when J or K is 1?
Me referring this video in 2024 where there are n no.of videos I find this video as best as it only req information
great job neso academy
Hi, thanks for the video. I have a question. Why is the truth table for an SR NOR gate flip flop when the SR flip flop in the diagram is a NAND type? Thank you.
Exactly. I was confused as well. Can someone explain?
thanks sir.
that's so better explained as compared to others
Can u recommend textbook on digital electronica
Sweet voice sir😁
Whether the race around condition is the output Qn cannot be predicted at the end of the clock pulse.?
Man, you are awesome.
Sir can you make a series of videos on 8085 microprocessor please!!!...and thank you for your existing content too
Thank u sir a very good explanation
THANKS A LOT, ITS JUST GOT ME READY.
I read in book that there are 2 nand gates more with srflipflop for converting it to JK flipflop
Great explaination and unorthodox English ❤😅
I m watching almost every 6 months
Why we wrote Qn bar in next state column when both inputs are 1??
I noticed he mistakenly put truth table for the SR latch using NOR gates, but in the video he used SR latch using NAND gate. If u watch the video about the SR latch, u will noticed his mistake.
The output should be memory when the input is 1 and 1 if we use NAND gates
Pls correct me if im wrong
No mistake is there in this video, please check the circuit again.
@@nesoacademy I've watch the video about SR Flip-flop, now I realize my mistakes. Tq Sir for the reply.
@@nesoacademy All explanation in all video regarding Flip-flop really helps me a lot. Tqvm for the video.
i have learned so much things from you thank youu you are the best
light hearted joke with no hate: It seems like you were also 'racing' to finish the video asap 😁
You should correct this video, it is confusing.
If your talking about RS FF the memory state is "00" and "11" is forbidden state.
The memory condition in SR FF is "11" and "00" is the not used one.
Thanks
Hi Neso Academy, your videos are really help full, thanks for the easy explanations.
for the JK flip flop i have a question, why are we considering the output of clk, S and R as Q(n+1) and why not just Q?
this is causing a lot of confusion since the value iof Q and Q(n+1) are opposites. please help !!
Both are same
yes
What is the flip-flop definition
sir I think there is a mistake. during the second round you have 1 at the input of upper right nand gate and 0 through Qbar. so the output should be 1and not 0. please explain. thank you
Yes . The guy messed up there .
5:20, You said for SR(0,1) output is (Q = 1, Q' = 0) for NAND SR. Then in SR FF video, you said that when SR FF is implemented using NAND gate then, (0, 0 ) is 'not used' condition. But here, you are saying that 1,1 is not used condition even though its NAND gate.
SR NAND Latch truth table
S R Q
0 0 Not used
1 0 0
0 1 1
1 1 Memory state
Can you please explain how and why ?
Esne confuse kr diya hai aapko dusra video dekhna pdega.. Truth table nor ka hai example ckt nand ka.. Ckt desigh bhi RS ki jaga SR ka h.. Avoid this video!
At 4:44, why is the clock always 1?
No matter what we input if the clock is 0 then we will get the memory (previous) output