@@last_time_I_pooped_was I'm a working electrical engineer and pursuing my PhD. As an added note, I've never mentioned, used, or required knowledge about JK flip-flops since the computer engineering course at the time of the above comment. Everything is based on the D flip-flop.
I have tried to understand JK flipflips for 15 years now and FINALLY I understand what they are, An SR latch with an extra feature ! TOGGLE. My goodness, THANK YOU !!
I had digital electronics paper today..al I did ystrdy was watching ur videos.and im nw here typing my gratitude. thank you so much brother...you have brought satisfaction in me.cos I really feel having learned something.
After doing a couple of hour of observation and trying different combination of gates for flip-flop I came up with these conclusions. Things get really confusing when we moved to the J-K flip flop. Let’s start from beginning, We’ve two data storing elements i.e. 1: SR NOR Latch 2: SR NAND Latch They work the same but their truth tables are completely opposite to each other. i.e. SR NOR Latch truth table S R Q 0 0 Memory state 1 0 1 0 1 0 1 1 Not used SR NAND Latch truth table S R Q 0 0 Not used 1 0 0 0 1 1 1 1 Memory state After studying these basic memory elements. We moved to SR latches with “enable”. This enable is input to the two NAND gates along with Set and Reset (as in the circuit diagram shown in video). The output of these two NAND gates is input to the Latch (SR NAND). If we replace “enable” by “Clock” we would have a flip flop. Let me ask you a question. Can’t we use any other combination of gates? Of course, we can. See the possible combinations which will work as an SR flip flop. 1. AND-NOR 2. NOR-NOR 3. OR-NAND 4. NAND-NAND (Used in video) You must be thinking what about the other combinations? 5. NAND-NOR 6. OR-NOR 7. AND-NAND 8. NOR-NAND These combinations (5 to 8) will not work as flip flop. Try making truth table for each of these combinations. After making truth table, You’ll realise that these circuits (5 to 8) are automatically going into “Invalid State” when the clock is Low/High depending upon the circuit configuration. Flip flop must follow one property, if clock goes Low or High, it must have a memory state. See these circuits are not storing data we can’t use these combinations. The only possible combinations which will work as an SR flip flop are: 1. AND-NOR 2. NOR-NOR 3. OR-NAND 4. NAND-NAND (Used in video) Hope, it cleared your doubt till now. But as we move to J-K and T flip flop. We again have some limitations. We get J-K flip flop when we feedback Q’ to the top NAND gate and Q to the bottom NAND gate Using this type of arrangement of feedback. Only two possible combinations will work i.e. 1. NOR-NOR 2. NAND-NAND Did you see? We started with 8 combinations and end up having only two useful combinations for J-K and T flip flop. If you want to use the remaining combinations for J-K and T flip flop 1. AND NOR 2. OR NAND Then, these two combinations can also be used if we make some changes in the feedback arrangement. Suppose, if we have an AND-NOR SR flip flop we want to make JK flip flop then we have to use this configuration, “If Q is input to the top AND gate and Q’ is input to the bottom AND, using this configuration the remaining two (AND-NOR, OR-NAND) will also work.” I tried every possible combination and their truth table. Everything in this video is correct and accurate. Hope it helped you!
your stuff is kinda wrong in terms how it is tought in my school. Here truth tables are the same with any gates, what changes are the inputs and the scheme IE in SR latch with nand if you give top input s and bottom input r while top output is q then you will get the opposite of regular truth table however in my university that is considered a nonsensical trigger. You have to give both inputs reversed, so top input is 'not s' bottom is 'not r' ;;;; outputs: top 'q' bottom 'not q' though there are other combination where the table would be correct as well IE nR->nQ nS->Q and only difference of sr and jk is the 11 in sr is undefined and in jk is reversed.
for anyone having trouble remembering this, i suggest you think of it like this: Only when Q = 1, the device can be Reset, and only when Qn = 1, the device can be set. Just as a tip for remembering it more easily 😊
Hi NESO, If Q is given back to J NAND gate Q' is given back to K NAND gate,Also toggiling occurs. You proved that you are good teacher.And you has a knowledge sharing great habit.🙋🏻♂️
Sir, I am very thankful to you for this.aapke lectures se Maine bahut ache marks obtained kiye.warna meri reappear thi sir electronic mein.thanks sir......
"you have already studied about the SR flip-flop and D flip-flop so what is the need to study the next type of flip-flop that is your third flip-flop" YES EXACTLY WHAT I'M THINKING, WHYYYY
That was a wonderful presentation! However, I do wanna point out that there are two main variations on the SR Latch (which are used to synthesize the JK Flip Flop)...refer to the previous video as self-evidence. WHY DOES THAT MATTER? ==>> The NOR type preserves the memory state of Q, Q_bar whenever S = R = ‘0’; S = R = ‘1’ results in the forbidden state. The NAND gate simply inverts the relationship, where all ‘0’ is forbidden and all ‘1’ is the memory preservation state. I noticed that the SR schematic is NAND based, whereas its truth table is NOR based...an alleged contradiction, if you will. I’m not a seasoned pro at this, but I think my observation makes sense, and can be used to improve the insight that you provided. Again, great video, (& to the viewers, take the presentation with a grain of salt). :) I’ll keep watching, Neso Academy. Have a great day!
Here,T.T. for SR f/f using NOR gate and and the diagram for RS f/f using NAND gate, which is quite overwhelming if you are looking table and the diagram parallely , so nerds don't get confused 😕
00:06 JK flip-flop provides an advantage over SR and D flip-flops. 00:51 Introduction to JK flip-flop 01:42 The JK flip-flop has two outputs Q and Q complement. 02:50 JK flip-flop and SR flip-flop have similar outputs except for the last case. 04:06 Analyzing the values for Q and Q complement 05:03 NAND SR latch can produce different outputs based on input changes 06:01 The JK flip-flop races between 0 and 1 06:58 JK flip flop output is the complement of the previous state.
He was actually replying to some other person's comments. But it seems like that other person has deleted his comments and this conversation looks one sided.
If I assume Qn-1 = 1 and ~Qn-1 = 0, and I also set c=1, j=1 and k = 0, then the Inputs of the last nand gates (so the one for the latch) are both 0 and 1, which would result in Qn =1 and ~Qn = 1 if you go and check the network (not the truth table).
Man, you are awesome. I'm studying for my test and you are the only guy that I understand! thank you so much for helping me. I'll drop my PayPal contribution on your website tomorrow. keep the great work!
thank you so much for putting this much efforts and making it very clear and I'm really hoping that you are going to upload the the sequential circuits designing and analysis and the state digram because I have exam this week and can't find any good resources
i also got confused but now figured it. The TT is for SR-FF : for this remember that SR FF consists of a SR Latch. Here the inputs are S,R for the FF, but the inputs of the embedded SR Latch are S* , R*. So if you consider the TT with the inputs as S*, R* then the Qn+1 values satisfies the SR NAND latch TT.
U don't but if u see the nand truth table when ever one input is 0 then irrespective of 2 input we can say the output will always be 1.so if J=0 and K=1(0,1) input we take the Q=1 and then we pass this 1 as 2nd input of k and thus ~Q =0. Hope this help
I'm repeating an electronic course, I got 7% as my Class Test 2 mark(i got 0 on the topic about Latches, flipflops and 555 timer)and I was following the lecture trying to be a good kid, thinking bunking classes is bad, only to find a random 7 minites video on TH-cam that made me understand something that I've been struggling to understand for 6 months, wtf🤧. I think we're getting scammed. I'm not even sure that I'll be able to make back the tuition fee money. I will have to work for more than 7 years to make it back. And that's mad because if you're someone who has a school debt, you'll have to work for 5 to 7 years,working for nothing but the school debt. the only way to cover the amount faster is to have a side hustle or just start a company, and if you do that, that would mean you wasted 4 or 5+ years in engineering school. These universities or colleges are running businesses on us.
In J-k flip flop you have made use of 3 input NAND gate with 1.J 2.clk and 3 .k Until and unless we get all.3 input how will the gate work or there is previous some Q and Q bar going in 3 input NAND gate , please clarify it
You guys are confusing the basic SR latch truth table, with the full SR flip flop truth table (which has two extra NAND gates)... S* and R* were shown in the truth table you are confused by. The addition of the two NANDs at the left side means S* and R* are inverted relative to what you saw before. So it makes it clearer actually, as S means set finally and R means reset, for values of 1.
I noticed he mistakenly put truth table for the SR latch using NOR gates, but in the video he used SR latch using NAND gate. If u watch the video about the SR latch, u will noticed his mistake.
Bro had a mistake, S=1, R=1 works as memory and S=0, R=0 is not used in case of SR flip flop when the NAND latch is used , you must use NOR latch for that in the cross coupling section 🤔🤔🤔🤔
I don't know why you have choosen as Q and Q complement different in last case... What does the meaning of last state if you taken as Different ? I don't know why... But I think there should be some different explanation to it....
NESCO ACADEMY THERE IS A MISTAKE AT 3:00 when the case is j=1,k=0 you just assumed j=S and k=R saying that the truth table is same for JK and SR , you didn't derive JK truth table and proved it is same.
Wow great but it's modified form of Sr and d it use two inputs and invalid condition not occur also these working in a proper way actually compliment to each other
sir in the sequential circuits playlist, you haven't added video of characteristic and excitation table of d flip flop.You directly moved onto JK flip flop. Please add it to the playlist too.
Learned more in 20 minutes of these videos than a full month in my CMP ENG course. Life saver.
Now what are you doing in ur life?
@@last_time_I_pooped_was I'm a working electrical engineer and pursuing my PhD.
As an added note, I've never mentioned, used, or required knowledge about JK flip-flops since the computer engineering course at the time of the above comment. Everything is based on the D flip-flop.
@@last_time_I_pooped_was i was wondering this too
how in the world did you not learn about flip flop circuits
Pretty Dumb I guess
I have tried to understand JK flipflips for 15 years now and FINALLY I understand what they are, An SR latch with an extra feature ! TOGGLE. My goodness, THANK YOU !!
I had digital electronics paper today..al I did ystrdy was watching ur videos.and im nw here typing my gratitude. thank you so much brother...you have brought satisfaction in me.cos I really feel having learned something.
After doing a couple of hour of observation and trying different combination of gates for flip-flop I came up with these conclusions.
Things get really confusing when we moved to the J-K flip flop.
Let’s start from beginning,
We’ve two data storing elements i.e.
1: SR NOR Latch
2: SR NAND Latch
They work the same but their truth tables are completely opposite to each other. i.e.
SR NOR Latch truth table
S R Q
0 0 Memory state
1 0 1
0 1 0
1 1 Not used
SR NAND Latch truth table
S R Q
0 0 Not used
1 0 0
0 1 1
1 1 Memory state
After studying these basic memory elements. We moved to SR latches with “enable”. This enable is input to the two NAND gates along with Set and Reset (as in the circuit diagram shown in video). The output of these two NAND gates is input to the Latch (SR NAND). If we replace “enable” by “Clock” we would have a flip flop.
Let me ask you a question. Can’t we use any other combination of gates?
Of course, we can.
See the possible combinations which will work as an SR flip flop.
1. AND-NOR
2. NOR-NOR
3. OR-NAND
4. NAND-NAND (Used in video)
You must be thinking what about the other combinations?
5. NAND-NOR
6. OR-NOR
7. AND-NAND
8. NOR-NAND
These combinations (5 to 8) will not work as flip flop. Try making truth table for each of these combinations. After making truth table, You’ll realise that these circuits (5 to 8) are automatically going into “Invalid State” when the clock is Low/High depending upon the circuit configuration. Flip flop must follow one property, if clock goes Low or High, it must have a memory state. See these circuits
are not storing data we can’t use these combinations.
The only possible combinations which will work as an SR flip flop are:
1. AND-NOR
2. NOR-NOR
3. OR-NAND
4. NAND-NAND (Used in video)
Hope, it cleared your doubt till now.
But as we move to J-K and T flip flop. We again have some limitations.
We get J-K flip flop when we feedback Q’ to the top NAND gate and Q to the bottom NAND gate
Using this type of arrangement of feedback. Only two possible combinations will work i.e.
1. NOR-NOR
2. NAND-NAND
Did you see? We started with 8 combinations and end up having only two useful combinations for J-K and T flip flop.
If you want to use the remaining combinations for J-K and T flip flop
1. AND NOR
2. OR NAND
Then, these two combinations can also be used if we make some changes in the feedback arrangement.
Suppose, if we have an AND-NOR SR flip flop we want to make JK flip flop then we have to use this configuration,
“If Q is input to the top AND gate and Q’ is input to the bottom AND, using this configuration the remaining two (AND-NOR, OR-NAND) will also work.”
I tried every possible combination and their truth table. Everything in this video is correct and accurate.
Hope it helped you!
your stuff is kinda wrong in terms how it is tought in my school. Here truth tables are the same with any gates, what changes are the inputs and the scheme
IE in SR latch with nand if you give top input s and bottom input r while top output is q
then you will get the opposite of regular truth table however in my university that is considered a nonsensical trigger. You have to give both inputs reversed, so top input is 'not s' bottom is 'not r' ;;;; outputs: top 'q' bottom 'not q'
though there are other combination where the table would be correct as well IE
nR->nQ
nS->Q
and only difference of sr and jk is the 11 in sr is undefined and in jk is reversed.
Wow great..... excellent understanding
😨
thanx saved me a lot of time
Bhai logic gates ki sale lagi thi kya
I dont understand .why it is getting dislikes..you are getting a great job sir..with a great teaching
because he calls latches flipflops
There are teacher of our college who didn't explain
@Prateek Patel okay. I'll watch .
Dislike are from those teachers who were expelled for not teaching well...
TH-cam removed dislike are you happy now ?
for anyone having trouble remembering this, i suggest you think of it like this: Only when Q = 1, the device can be Reset, and only when Qn = 1, the device can be set. Just as a tip for remembering it more easily 😊
At 2:04 we have the truth table for Sr ff with nor gate but we are using the diagram of Sr with nand gate these two totally gives different outputs
yes same doubt..
that is sr filp flop with NAND gate and that is correct. you are talking about sr latch with nor gate.
Man, i just wanna thank you for your videos, they helped me out in Varsity...i graduated last year but, Thank you so much💪💪❤
Hi NESO,
If Q is given back to J NAND gate
Q' is given back to K NAND gate,Also toggiling occurs. You proved that you are good teacher.And you has a knowledge sharing great habit.🙋🏻♂️
Sir, I am very thankful to you for this.aapke lectures se Maine bahut ache marks obtained kiye.warna meri reappear thi sir electronic mein.thanks sir......
"you have already
studied about the SR flip-flop and D flip-flop so what is the need to study the next type of flip-flop that is your third flip-flop"
YES EXACTLY WHAT I'M THINKING, WHYYYY
That was a wonderful presentation! However, I do wanna point out that there are two main variations on the SR Latch (which are used to synthesize the JK Flip Flop)...refer to the previous video as self-evidence. WHY DOES THAT MATTER? ==>> The NOR type preserves the memory state of Q, Q_bar whenever S = R = ‘0’; S = R = ‘1’ results in the forbidden state. The NAND gate simply inverts the relationship, where all ‘0’ is forbidden and all ‘1’ is the memory preservation state. I noticed that the SR schematic is NAND based, whereas its truth table is NOR based...an alleged contradiction, if you will. I’m not a seasoned pro at this, but I think my observation makes sense, and can be used to improve the insight that you provided. Again, great video, (& to the viewers, take the presentation with a grain of salt). :) I’ll keep watching, Neso Academy. Have a great day!
+Oswald Chisala this is really confusing me how can we use NAND based rs F-F while using NOR based f-f ??
Here,T.T. for SR f/f using NOR gate and and the diagram for RS f/f using NAND gate, which is quite overwhelming if you are looking table and the diagram parallely , so nerds don't get confused 😕
Sir you are a legend. I hope you get very successful in your life!
PLEASE MAKE VIDEOS ON DIGITAL LOGIC FAMILIES (TTL, ECL, CMOS etc) and ADC and DAC conversions.
Your lectures are great.
Thank you so much for them.
he wouldve done them if you weren't screaming at him. thanks a lot.
u r simply amazing! i hope you get all the success u deserve
00:06 JK flip-flop provides an advantage over SR and D flip-flops.
00:51 Introduction to JK flip-flop
01:42 The JK flip-flop has two outputs Q and Q complement.
02:50 JK flip-flop and SR flip-flop have similar outputs except for the last case.
04:06 Analyzing the values for Q and Q complement
05:03 NAND SR latch can produce different outputs based on input changes
06:01 The JK flip-flop races between 0 and 1
06:58 JK flip flop output is the complement of the previous state.
EE101
thank you :3
explained....the whole concept in a very simple manner,..... thank u sir.....
Just discovered these lectures. Now I don't have to worry about my CC V
First time i understood toggling. You are legendary man🙏
Thank u sir for providing such a nice explanations on the sequential circuits..it is really helpful to Me..
type sht
sir ,i have been hearing your voice by this tutorial ,i just i want to see your face ,your tutorials are really awesome
see you are crossing in my way
did i do anything to u
i just like that video whats wrong with that . You said "gay" that was really annoyed me
so sry if i hurt You.plz dont cross my way.
He was actually replying to some other person's comments. But it seems like that other person has deleted his comments and this conversation looks one sided.
Is it confusing only for me? :(
Yes
If I assume Qn-1 = 1 and ~Qn-1 = 0, and I also set c=1, j=1 and k = 0, then the Inputs of the last nand gates (so the one for the latch) are both 0 and 1, which would result in Qn =1 and ~Qn = 1 if you go and check the network (not the truth table).
U are correct
For all those saying the truth table is wrong, its NOT. The truth tables of NOR SR Latch and NAND SR Flip flop are almost similar.
I wish i found this channel sooner. finals are coming up.... gonna watch a few vids to save my grade loool
Thankuuuuuu sir
You really help us alot.
Clear concepts in a seconds.
You really make difficult subjects easy.
Man, you are awesome. I'm studying for my test and you are the only guy that I understand!
thank you so much for helping me.
I'll drop my PayPal contribution on your website tomorrow. keep the great work!
thank you so much for putting this much efforts and making it very clear and I'm really hoping that you are going to upload the the sequential circuits designing and analysis and the state digram because I have exam this week and can't find any good resources
Thnku so much for making this things so easy for us☺ u were a life saver to me😊
Thank you so much sir. You are simply marvelous.
Thanks again and again sir for your work
His way of teaching makes me feel like... It's an offline class. Mean face to face.
Tq sir.this videos are very usefull to me.any one cam understand ur lecturing easily. Way of teaching i loved it thanq sir
Your lectures are very helpful.
flip flop is too confusing to understand ngl
1:00 Why does the logic diagram represents a SR flip-flop with NAND gate but the truth table is of a NOR gate SR flip-flop?
exactly. confused me too.
i also got confused but now figured it.
The TT is for SR-FF : for this remember that SR FF consists of a SR Latch. Here the inputs are S,R for the FF, but the inputs of the embedded SR Latch are S* , R*.
So if you consider the TT with the inputs as S*, R* then the Qn+1 values satisfies the SR NAND latch TT.
light hearted joke with no hate: It seems like you were also 'racing' to finish the video asap 😁
😎😎Legends watching this after 6 years 😎😎😎😎
I think i am ultra legend then i am watching it after 9 years
@@Learn_from_Zero24 Lol same here
+ Neso Academy how did u know what is the value of Q and Q' , accept the last case where u assumed
U don't but if u see the nand truth table when ever one input is 0 then irrespective of 2 input we can say the output will always be 1.so if J=0 and K=1(0,1) input we take the Q=1 and then we pass this 1 as 2nd input of k and thus ~Q =0.
Hope this help
Great Explanation, one in a million!
Thank you very much!
I understood the concept well thank you so much sir👍
I m watching almost every 6 months
Congratulations 👏👏🎊 sir for 1million subscribers , keep growing
Uyyyy7w
are you trying to tell me, with a JK flipflop and two high inputs, it will flipflop?
Madness!
PS, actually very helpful. Thankyou :)
Wow, your presentation was really helpful! Thanks :)
To the legend who found this tutorial 20mins before exam
Happy teacher's day...Sir. Your videos helps me a lot. Please make video on electromagnetic.
Me referring this video in 2024 where there are n no.of videos I find this video as best as it only req information
great job neso academy
THANKS A LOT, ITS JUST GOT ME READY.
I'm repeating an electronic course, I got 7% as my Class Test 2 mark(i got 0 on the topic about Latches, flipflops and 555 timer)and I was following the lecture trying to be a good kid, thinking bunking classes is bad, only to find a random 7 minites video on TH-cam that made me understand something that I've been struggling to understand for 6 months, wtf🤧. I think we're getting scammed. I'm not even sure that I'll be able to make back the tuition fee money. I will have to work for more than 7 years to make it back. And that's mad because if you're someone who has a school debt, you'll have to work for 5 to 7 years,working for nothing but the school debt. the only way to cover the amount faster is to have a side hustle or just start a company, and if you do that, that would mean you wasted 4 or 5+ years in engineering school. These universities or colleges are running businesses on us.
thanks sir.
that's so better explained as compared to others
Explaination method is excellent
Thanks sir, All your lectures are well explained. Thanks :)
In J-k flip flop you have made use of 3 input NAND gate with 1.J 2.clk and 3 .k
Until and unless we get all.3 input how will the gate work or there is previous some Q and Q bar going in 3 input NAND gate , please clarify it
the truth table used is related to nor gater SR latch and you draw and explain all the video using the nand gates SR latch !
i also agree with omer..plz explain
he is using the truth table of nand, not that of nor
you are confusing between sr flip flop and latch
You guys are confusing the basic SR latch truth table, with the full SR flip flop truth table (which has two extra NAND gates)... S* and R* were shown in the truth table you are confused by. The addition of the two NANDs at the left side means S* and R* are inverted relative to what you saw before. So it makes it clearer actually, as S means set finally and R means reset, for values of 1.
sir used clocked s R flip flop using nand gata.
it is correct
Sir can you make a series of videos on 8085 microprocessor please!!!...and thank you for your existing content too
Great explaination sir I was totally understanded thank you for sharing this sir♥️👌
J and K inputs should be swapped. When J goes high, we should see Q output high, and in your video it is opposite (wrong)
no comments you are the best
Thank you so much, sir.
Man, you are awesome.
for me this tutorial is so good good job
I think dislikers are University lectures.
I noticed he mistakenly put truth table for the SR latch using NOR gates, but in the video he used SR latch using NAND gate. If u watch the video about the SR latch, u will noticed his mistake.
The output should be memory when the input is 1 and 1 if we use NAND gates
Pls correct me if im wrong
No mistake is there in this video, please check the circuit again.
@@nesoacademy I've watch the video about SR Flip-flop, now I realize my mistakes. Tq Sir for the reply.
@@nesoacademy All explanation in all video regarding Flip-flop really helps me a lot. Tqvm for the video.
thanks to your video, i have understood now
you guys are great. iam able to understand about flip flops. good job. all the best guys and thank you : )
Don't you think so, that clk. Must be edge triggered (as per diagram) ?
salute to neso academy very good explanation
Bro had a mistake, S=1, R=1 works as memory and S=0, R=0 is not used in case of SR flip flop when the NAND latch is used , you must use NOR latch for that in the cross coupling section 🤔🤔🤔🤔
Yes bro same confusion
I think bro took wrong truth table
I don't know why you have choosen as Q and Q complement different in last case... What does the meaning of last state if you taken as Different ? I don't know why... But I think there should be some different explanation to it....
Excellent video!
i have learned so much things from you thank youu you are the best
Sir Can you please make videos on programming of 8051 microcontroller
It would help a lot of students.
Thank you.
Thank you sir for clarification toggle state
nice videos sir....i am completely understand ....one more thing is there is some MISTAKES while u r explaining....plz correct it
this was grately helpful. I had a hard time understanding toggling
THANK YOU
Thank you
NESCO ACADEMY THERE IS A MISTAKE AT 3:00 when the case is j=1,k=0 you just assumed j=S and k=R saying that the truth table is same for JK and SR , you didn't derive JK truth table and proved it is same.
It was really helpful
I apperciate your work!!!!
I read in book that there are 2 nand gates more with srflipflop for converting it to JK flipflop
Thank you sir🥺❤️
amazing job man! keep going !thanks for the help!
I think you are the reason for my success !!!!!
Thanks
شرح جدا واضح وبسيط .. Thank you
Great explaination and unorthodox English ❤😅
Oh my gosh!! That JK flip flop.....I thought Its sth Jungkook (BTS) flip flop 😑
Wow great but it's modified form of Sr and d it use two inputs and invalid condition not occur also these working in a proper way actually compliment to each other
simple to understand videos!
thank you so much sir
I must say, the truth table you are using is for flip-flop made out of NOR gates.
sir in the sequential circuits playlist, you haven't added video of characteristic and excitation table of d flip flop.You directly moved onto JK flip flop. Please add it to the playlist too.
thank you sir
Thank you sir
Thankyou
Sweet voice sir😁
isnt that a truth table for SR in a NOR?
Thanks brother
It is so helpful sir.Thank u