FPGA/SoC Board Bring-Up - QSPI (Zynq Part 3) - Phil's Lab #98
ฝัง
- เผยแพร่เมื่อ 17 ก.ค. 2024
- How to configure the QSPI Flash memory interface and create first-stage bootloader (FSBL) to automatically program a Xilinx/AMD Zynq system-on-chip on custom hardware. Schematic and hardware walkthrough, Vivado and Vitis configuration, and test.
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[TIMESTAMPS]
00:00 Introduction
00:51 Previous Videos
01:13 Altium Designer Free Trial
01:30 Schematic
02:45 Memory Choice (UG908)
03:53 PCB & Bootmode Pins
04:58 First-Stage Boot Loader (FSBL) Overview
05:39 Vivado Set-Up
06:57 Vitis FSBL & Boot Image
07:49 Vitis Hello World Application & Boot Image
09:14 Hardware Connection
09:53 Program Flash
11:44 Bootmode Selection (QSPI)
12:17 UART Hello World Test
12:26 Summary & What's Next
13:08 Outro - วิทยาศาสตร์และเทคโนโลยี
Informative, precise, fun to watch... One of the best electronics tutorials channels I've seen in a while
Thank you very much, Jonathan!
This is really cool. I've been looking into designing a board that has QSPI flash memory, although it is using a STM32 MPU instead of a Zync APU like in the video. Hopefully I can make a project like this one day. Awesome video as always Phil!!!
Thank you for your perfectly timed videos which lead me to modify my designs once again short before ordering the REV A batch 👌🏻.
Also when will your course be released? I cannot wait to learn how to design such advanced hardware!
Great video, favorite HW channel. When will your Zynq dev board be available for purchase?
Many Thanks
I got myself a Zynq based FPGA Board (Zynqberry) a while ago, but I couldn't get much out of it. I have some experience with former Altera Devices, but somehow i could not figure out how Vivado works, yet. This series helps a lot in drawing connections between Quartus Vivado and Altera Xilinx. Thank you.
Awesome, glad this is useful for trying out the Xilinx stuff!
Vivado and Quartus are pretty similar as they are doing the same thing, one big difference between Xilinx and Intel devices is the way clocks are handled. With Intel devices as long as you have the clocks on the right input pins Quartus does the rest for you. Xilinx devices are more flexible with clock inputs, but you have to worry about instantiating clock buffers etc internally yourself.
I like Xilinx parts, but the vendor lock-in on the tool chains always puts me off. It would be great if you could do an example of using open source tool chains for an FPGA based design. I know that limits your choices of parts and capabilities, but I'd really like to hear your experiences with that stack of tools because you also have experience with commercial tools so you can do a fair comparison.
Shawn Hymel over at DigiKey recently did a pretty good series of videos on just that. He used the open source APIO toolset to program a Lattice ICEstick.
Lattice's iCE40 and ECP5 stuff is usable with yosys and nextpnr if you're looking for a full FOSS development stack for FPGAs. You can also integrate FOSS HDLs with proprietary toolchains in some cases, e.g. using Amaranth with the Vivado toolchain to program certain Xilinx devices.
I don't know if it would be easily achievable or even possible to configure a Zynq using open source tools. Correct me if in wrong
I prefer to use an SD card over QSPI. Way faster and easier to update. The SD card can contain FSBL, FPGA bitstream and uboot/full linux system on a single partition FAT image. If you're worried about reliability an eMMC can store same and be updated from an SD.
Thanks for this video ❤❤❤, what’s the difference between booting from QSPI and SD Card?
qspi is memory component built on the board - usually used in deployment phase
sd card is external storage device - used in development phase
booting is quite the same for baremetal [only boot jumper changes]
in petalinux - qspi is relatively harder then sd card
Hey @PhilsLab, great video! Thanks! Please excuse the noob question, but at 2:18 you say that you add a "series termination resistor for the clock line in case I get any ringing or EMI problems" … have you mentioned elsewhere how you calculated this, or do you already have a video that covers this e.g., when you might need to add one, what values, etc.? Also when you talk about "high speed" signals, at what kind of speed does a signal become "high speed"?
Thanks! Series termination is based on something known as "reflected-wave termination", which is rather neat. I'm planning on making a video on various termination techniques, but for know check out Lee Ritchey's "Right The First Time" www.thehighspeeddesignbook.com (free) and the chapter on termination. The book/PDF will also answer your other question.
That's fabulous! Thanks @@PhilsLab. I'll look forward to your video! 👍
what interface do you use to program the memory? you mentioned JTAG . do you use the xilinx SmartLynq programmer?
Hello, thank you for the video. I have artix7 and IS25LP128 on my board. I saved data in IS25LP128 via microcontroller and want to read them from artix7. should I write my SPI code to send commands to IS25LP128 and read data? Should I write Quad SPI code when I select master spix4 in vivado (Tools, edit device properties, configuration mode)? can I boot flash via Tools, and generate memory configuration? I would be grateful if you explain me.
Very nice! Just noticed that the FSBL is stored on on-chip memory inside of the FPGA portion (presumably?), which is pretty neat... I didn't realize it had NV memory. Sucks that it's still so difficult to obtain any decent FPGAs still :( You must have gotten lucky to get those Zynq parts.
They are available (Mouser, Digikey, even Farnell, etc.)
The FSBL is stored in off-chip non-volatile memory (in this case, the QSPI FLASH) and then loaded into the Zynq's volatile OCM at boot.
And Zynqs are actually still available in quite a few places (Mouser, LCSC, ...)!
Hi Phil, can i ask you when the full course on Fedevel about this board will be available ?
Hey, I'm still working on it, but should be out in around June latest I hope.
why did you need to generate the BOOT image file for the fsbl application, if you only used the elf file of it for the flash programming? and did you programmed the qspi via jtag connection? thank you for the informative video
Yes QSPI is programmed via Jtag. BOOT.BIN with it's packaged images are required to boot the device.
Yeah you don't actually need to create BOOT image for the FSBL application. Simply building the FSBL project will generate the boot loader (.elf) file in the debug folder.
your video is so helpful! I follow ur step, but there have a error.
Problem in running uboot
Flash programming initialization failed.
ERROR: Flash Operation Failed
vitis log is here
cmd /C program_flash -f \
F:/hello_test_0825_001/hello_test_hewor_0825_system/_ide/bootimage/BOOT.bin -offset 0 \
-flash_type qspi-x4-single -fsbl \
F:/hello_test_0825_001/design_1_wrapper_1/export/design_1_wrapper_1/sw/design_1_wrapper_1/boot/fsbl.elf \
-blank_check -verify -cable type xilinx_tcf url TCP:127.0.0.1:3121
****** Xilinx Program Flash
****** Program Flash v2020.2.2 (64-bit)
**** SW Build 3118627 on Tue Feb 9 05:14:06 MST 2021
** Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
Connected to hw_server @ TCP:127.0.0.1:3121
Available targets and devices:
Target 0 : jsn-DLC9LP-0000100271d701
Device 0: jsn-DLC9LP-0000100271d701-4ba00477-0
Retrieving Flash info...
Initialization done, programming the memory
Using default mini u-boot image file - C:/Xilinx/Vitis/2020.2/data\xicom\cfgmem\uboot\zynq_qspi_x4_single.bin
===== mrd->addr=0xF800025C, data=0x00000000 =====
BOOT_MODE REG = 0x00000000
Downloading FSBL...
Running FSBL...
Finished running FSBL.
===== mrd->addr=0xF8000110, data=0x000FA240 =====
READ: ARM_PLL_CFG (0xF8000110) = 0x000FA240
===== mrd->addr=0xF8000100, data=0x0003C008 =====
READ: ARM_PLL_CTRL (0xF8000100) = 0x0003C008
===== mrd->addr=0xF8000120, data=0x1F001400 =====
READ: ARM_CLK_CTRL (0xF8000120) = 0x1F001400
===== mrd->addr=0xF8000118, data=0x000FA240 =====
READ: IO_PLL_CFG (0xF8000118) = 0x000FA240
===== mrd->addr=0xF8000108, data=0x0003C008 =====
READ: IO_PLL_CTRL (0xF8000108) = 0x0003C008
Info: Remapping 256KB of on-chip-memory RAM memory to 0xFFFC0000.
===== mrd->addr=0xF8000008, data=0x00000000 =====
===== mwr->addr=0xF8000008, data=0x0000DF0D =====
MASKWRITE: addr=0xF8000008, mask=0x0000FFFF, newData=0x0000DF0D
===== mwr->addr=0xF8000910, data=0x000001FF =====
===== mrd->addr=0xF8000004, data=0x00000000 =====
===== mwr->addr=0xF8000004, data=0x0000767B =====
MASKWRITE: addr=0xF8000004, mask=0x0000FFFF, newData=0x0000767B
Problem in running uboot
Flash programming initialization failed.
ERROR: Flash Operation Failed
Around 9:10, you show that you are creating a boot image. The fsbl, bitstream, and your application partitions are already created. Did Vitis do this for you, or had you already set it up previously? I tried following your steps, and it is failing for me on programming the QSPI. However, it is probably also due to trying to use Vitis 2023 which is completely different now.
Following up on this. The above was caused by me not exporting hardware with the bitstream. Also, I designed a board that didn't have DDR, which is required if you want to run the Zynq FSBL without modification.
This series is really nice. But aside from a the hint in the name I am dying to know what you envisioned with this board. A blog post will suffice…
Thanks! Basically just an 'educational development board', learning how to design the hardware, configure the board from the ground up, and then demonstrate how the Zynq can be used in various applications. Essentially, very similar to the videos I have on STM32 microcontrollers. For FPGAs/SoC I haven't found many resources showing everything from the ground-up and the learning curve is quite steep, so I'm trying to 'remedy' that.
@@PhilsLab any news on the course? I filled out your survey a few weeks ago.
Hey Phill ever thought of implementing Linux on your zynq board?
Hey, Yes, I'm working on that right now!
@@PhilsLab that's great to hear !
I'm doing my final year project and it's about a modular board, and surprisingly it's about the zynq7000 so as you can imagine you've been of great help to me, thank you !!!
also when will you be releasing your new course ? and is it about your zynq board ?
Awesome, glad the videos have been helpful - good luck with your project!
Course will still take a little while longer, as the content is just growing and growing... And yes, it'll discuss this board as well as general PCB/HW design techniques!
👍🙏❤
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