PCB High-Speed Delay Matching - Phil's Lab
ฝัง
- เผยแพร่เมื่อ 18 พ.ค. 2024
- Tips on PCB trace delay matching/tuning for high-speed interfaces. Covering basics, microstrip/stripline, differential pairs, timing margins, and practical tips. PCBs by PCBWay www.pcbway.com
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[TIMESTAMPS]
00:00 Introduction
01:10 Altium Designer Free Trial
01:33 PCBWay
01:54 Courses
02:08 Delay Matching Basics
03:29 Outer vs Inner Layer
05:50 Delay Calculator
06:30 Timing Margins
07:15 DDR Skew Spec & Derating
08:40 Same Layer/Transition Routing
11:25 Delay Tuning Example (Single-Ended)
13:55 Differential Pairs
15:29 Intra-Pair Tuning Example
16:16 Additional Tips
17:57 Package Delays
18:55 Outro - วิทยาศาสตร์และเทคโนโลยี
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Very good content! Great job describing a very complex routing! Liked and subscribed.
Wow. What great info. Well done, sir.
Very good video explaining a very complex subject. Liked and Subscribed!
Such a great job as always! Keep doing those advanced things, you don't know how helpful this material is. The best channel for PCB design and tips
Thank you very much, Alejandro!
Great video Phil, as always.
Thank you, Jim!
Great as always. I didn’t know about package delay and how to find it, so this was super valuable for me. Thanks Phil.
Thank you very much, glad it was useful!
Just like listening symphony ❤
Very advanced from where I'm as a hobbyist but enjoyed it. Well done.
Thanks, Tamer!
Great as always. I am passionate about PCBs design because of you. Thanks you.
recently, I will be join in your course.💪
Thank you, Surasak!
Great explanation Phil! Thanks for the just-in-time video as I was about to make board with USB High Speed
Thank you - glad the timing worked out!
Yet another great video!
Thank you!
another great video .. your videos are very very usefull from the si and pi point of view they are full of interesting topics
thak you for your job
Just got paid today so Im going to purchase your new course (already finished the mixed signal course it was very good). Another great video!
Thank you very much for your support. Great to hear you liked the first one!
Thank you very much!
Thanks for watching!
Thank you, very good information
Thanks for watching!
What a neat explanation! I admire you, Phil. I am from Ecuador and I would love to work someday with you 😊
Thank you very much, Teddy! Well who knows maybe someday we can make that happen :)
Thank you for a great video. I’m designing a board with a fpga and ddr4 memory and the delay matching is something that guy tells me is the way to design rather than length matching outside the packages.
Thanks, Fredrik - hope all goes well with your FPGA + DDR4 design!
This is amazing! So much detail in a compact to-the-point format. Been learning from you for a long while now, but don't think I actually ever replied. Sorry for that, but thank you for your tutorials! Not that I think I really will need this in the coming future, as my EE structures are generally much larger and more basic, but you explained it in such a way that even this mechanical engineer understood it! 😁
Oh, just a curiosity, but if you'd come across a situation where space constraints made meandering paths impossible, would it be possible to create delays using ceramic capacitors and/or inductors?
Thank you very much for your kind comment and thanks for watching :)
For high-speed systems, I'm afraid that wouldn't work (space-constraints, degradation of signal integrity, etc.). Even in very space-constrained systems you can usually make it work (HDI, increased layer count, etc.).
What about a video on HDMI hardware design? 😊
Great!
Thanks!
Thank you very much for all those videos.., I was wondering do u have any advice on how to prevent short circuits when making a custom PCB with a laser or with acid?
This video was great.. I am really thinking about checking out Altium. I used to use Eagle. Switched to KiCad as it was free and just as good. I had heard Altium is next level and was always curious about it. Your videos using Altium are really pressuring me to grab it. Great content as always!
PS: Does KiCad have support for match delays? I never really had to play with match delays much as my stuff is usually simple and such things are rarely necessary.
Great Video as always. It is good if you can do design walkthrough of a educational FPGA like tiny fpga, tang nano 9k.
I am just getting started with his FPGA course. Its pretty good and detailed. The things you learn will translate to other FPGA platforms. Good investment imo.
Thanks! I have a few FPGA-based hardware design walkthroughs on the channel.
Very interesting! But by seeing that "scary" meanders, don't they add inductance and capacity, which changes propagation delays again? Or does it get considered in the calculation process?
Great video !! Thanks for putting all those useful tips out there ! :) Considering the large (nearly 10% ?!) delay difference between signals on inner & outer layers, how does this affect return paths? If I have the signal on an outer layer and its reference ground plane in the layer right below, does the speed difference have any impacts there? if the trace is 2cm, the difference between the two is 12 ps, so I'm wondering if we'd see any nasty side-effects at the other end?
Also, you mentioned meanders for differential pairs matching should be placed close to the pads, I would intuitively think it'd be better to "distribute" them evenly so the signal edge on both lines would always be rougly in the same spot, but indeed it would cause impedance mismatches along the line, no idea how bad this can be? Would you say it's OK to distribute them on either side instead? like if I have to place 2 squigglies to match the delays, should I place one on one end, and the 2nd on the other end? or does this introduce more nastyness than it solves?
Thanks for all the informative content, learned a lot watching your videos
Thank you!
Regarding the return paths and propagation speed differences, there's no particular downside as far as I'm aware. For controlled impedance however, the critical length does change depending on outer vs inner layer, so that would be an important takeaway.
If the length/skew mismatch is short, then yes, ideally the intra-pair meanders should be placed where the mismatch happens. However, this is rarely practical and therefore the intra-pair matching is typically placed closed to an impedance discontinuity.
Hi Phil,
In my custom board the DDR3L runs without an issue at 303mhz. But when i increase to 533.33mhz it fails. Even for 333mhz and 400mhz it is inconsistent.
1) there is more than 10ps between some address lines wrt clock
2) DM pins randomly goes -ve at high frequencies
But I was unable to pin point the issue.
If you have faced or seen something similar please guide me here
Hi, do you have any tips for if you've run out of room to add the delays?
cool!
Thanks!
Design is one thing, reality is another. How do you test your prototype to make sure its correct?
Check out the board bring-up series for the ZettBrett, which goes over testing & verifying all interfaces of the real-world system: th-cam.com/play/PLXSyc11qLa1ZutrEG2XmyWrNz17SSQTdH.html
@@PhilsLab Thanks. Off to have a look ...
Hi, Phil !
I'm asking about discount for students over "mixed signal pcb design" course on fedevel academy
Hi phill could you please make detailed course on EMI/EMC ,Signal Integrity and power integrity
Hey, check out Fedevel Education (marketplace.fedevel.education/). There are many courses on EMI/EMC, SI, PI there.
Can you please share these files? The link you've provided does not have these files. Please respond Mr. Phil
Hello sir could you please make a video on GPS module design please
On integrating a GPS module, or creating a GPS module?
@@PhilsLab Creating a GPS module and interfacing it with MCU
Hi Phil's I'm from India and i wanted to do Mixed signal Hardware Design Course, what is procedure for it
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