A good future video would be to go over the details of how each IO pin of the FPGA works. Pretty sure they all have a rail-to-rail clocked comparitor to support all the differential logic standards. Most have a lot of output drive strength settings. Many also have a variable delay line and 4-bit shift register for serial to parallel conversion so 1Gbps signals on the IO can be slowed down for the fabric. All these features add a LOT of analog capability to the IO pins that's only indirectly documented.
Great video. One remark about PUDC_B though: PUDC_B (Pull-Ups During Configuration (Bar)) controls the state of the FPGA IOs *during configuration* (i.e. while the FPGA is programmed), not the default/startup value of the FPGA IO pins. It is also not possible to pull the FPGA IOs low during configuration; if PUDC_B is tied low, all IOs will have pull-ups during configuration; if PUDC_B is tied high, all IOs will be in a high-Z state.
Hi, in 07:44 bootmode in my sight is set to 101 which is JTAG (or 100 when removing the 0R) , but it is said in the video that it is master SPI mode (that is 001). I can't get that !? It seems that the order of M0, M1, and M2 is reveresed
Hey Philip, nice Video! Really quite useful with lots of information. Regarding the power on sequence I would have a concern. As you mentioned the threshold is only 400mV for the enable circuit. When turning on a subsequent voltage this voltage may not be properly stabilized by the time you turn on the next rail. A small RC circuit for the enable of the next voltage would probably mend this and allow the previous rail and circuits inside to power up fully before the next rail is turned on. Happy to hear your thoughts on this. Keep up the great work and looking forward to the next video!
Hey Deniz, That's right - it may be beneficial to add a small cap to the enable pin which is fed through a resistor from a buck's output voltage. However, usually for designs like these I'd use a quad buck converter that has power good signals for each channel - this way we wouldn't need to add a delay. For this design I happen to have had some of the ICs lying around and thought I should use them (despite only having a 'power good all' signal).
So simple 😂 But it's Phil's Lab. No wonder why I feel familiar with the choice of Artix-7 A35T variant that he also used in his previous video on FPGA M.2 board.
Do you have any tips for creating the symbol and footprint for a BGA part? Not all parts and companies supply these. Does Altium have a way to import pins from an excel sheet? Moreover, do you have any tips or tricks to employ to verify a symbol/footprint?
There are a couple other videos on the channel: th-cam.com/video/enGV58pIvXs/w-d-xo.html th-cam.com/video/NTrP3fDrViQ/w-d-xo.html On the Altium blog, there is an article from Mark Harris titled "Creating High Pin Count Schematic Symbols Quickly" that shows a way to make large symbols with many pin names that shows one way to do it from a table.
Great video Phil. You have mentioned that you haven't used a few of the FPGA banks. Yet you still delivered them power as well as placed decoupling caps. Is that really necessary?
Hey Phil, great job, thanks for the useful tutorial. I wonder how to create a board support package, do you think to prepare kinda bsp tutorial? (may be its not to do with the altium , so you can show it in you personal channel)
Thanks, Mustafa! I recently received some FPGA/SoC boards from manufacturing and am in the process of doing exactly that - creating BSPs. As you said, this'll be something for my personal channel in the next few months :)
Hey, it's Phil's Lab!!!!
So much useful information in one video! Philip, thank you so much! Looking forward to your next episodes!
Thank you very much, Pavel!
Keep up the videos with Phill. Great content as always.
Thank you very much!
You are fantastic. Thank you so much for the video!
A good future video would be to go over the details of how each IO pin of the FPGA works. Pretty sure they all have a rail-to-rail clocked comparitor to support all the differential logic standards. Most have a lot of output drive strength settings. Many also have a variable delay line and 4-bit shift register for serial to parallel conversion so 1Gbps signals on the IO can be slowed down for the fabric. All these features add a LOT of analog capability to the IO pins that's only indirectly documented.
Noted
Thanks for cool necessary information
That's a cool project. This was a very informative and helpful video. Will you show us how you did the BGA routing?
Thanks! Yes, I'm going to go over a few aspects of the PCB design for this board in future videos.
Excellent Video
Glad you enjoyed it
Nice, thanks 🎉
Brilliant, Thank you.
Glad you enjoyed it!
Thanks, Lee!
Great video. One remark about PUDC_B though: PUDC_B (Pull-Ups During Configuration (Bar)) controls the state of the FPGA IOs *during configuration* (i.e. while the FPGA is programmed), not the default/startup value of the FPGA IO pins. It is also not possible to pull the FPGA IOs low during configuration; if PUDC_B is tied low, all IOs will have pull-ups during configuration; if PUDC_B is tied high, all IOs will be in a high-Z state.
Thanks, Andreas - that's a great point!
Hi, in 07:44 bootmode in my sight is set to 101 which is JTAG (or 100 when removing the 0R) , but it is said in the video that it is master SPI mode (that is 001). I can't get that !? It seems that the order of M0, M1, and M2 is reveresed
The description is M[2:0], so 001 means M2=0, M1=0, M0=1
Hey Philip, nice Video! Really quite useful with lots of information.
Regarding the power on sequence I would have a concern.
As you mentioned the threshold is only 400mV for the enable circuit. When turning on a subsequent voltage this voltage may not be properly stabilized by the time you turn on the next rail.
A small RC circuit for the enable of the next voltage would probably mend this and allow the previous rail and circuits inside to power up fully before the next rail is turned on.
Happy to hear your thoughts on this.
Keep up the great work and looking forward to the next video!
Hey Deniz, That's right - it may be beneficial to add a small cap to the enable pin which is fed through a resistor from a buck's output voltage. However, usually for designs like these I'd use a quad buck converter that has power good signals for each channel - this way we wouldn't need to add a delay. For this design I happen to have had some of the ICs lying around and thought I should use them (despite only having a 'power good all' signal).
So simple 😂
But it's Phil's Lab.
No wonder why I feel familiar with the choice of Artix-7 A35T variant that he also used in his previous video on FPGA M.2 board.
Do you have any tips for creating the symbol and footprint for a BGA part? Not all parts and companies supply these. Does Altium have a way to import pins from an excel sheet? Moreover, do you have any tips or tricks to employ to verify a symbol/footprint?
There are a couple other videos on the channel:
th-cam.com/video/enGV58pIvXs/w-d-xo.html
th-cam.com/video/NTrP3fDrViQ/w-d-xo.html
On the Altium blog, there is an article from Mark Harris titled "Creating High Pin Count Schematic Symbols Quickly" that shows a way to make large symbols with many pin names that shows one way to do it from a table.
Great video Phil.
You have mentioned that you haven't used a few of the FPGA banks. Yet you still delivered them power as well as placed decoupling caps. Is that really necessary?
cool video, but honestly you just intimidated me with starting FPGA circuits ... ^^
Does Altium have an FPGA IO unraveling tool similar to Mentor Graphics' Xpedition IO Optimizer? If so, is there a video covering this tool?
Hey Phil, great job, thanks for the useful tutorial.
I wonder how to create a board support package, do you think to prepare kinda bsp tutorial? (may be its not to do with the altium , so you can show it in you personal channel)
Thanks, Mustafa! I recently received some FPGA/SoC boards from manufacturing and am in the process of doing exactly that - creating BSPs. As you said, this'll be something for my personal channel in the next few months :)
Why did I not have such tutorials 10 years ago? Most of my life has been ruined.
👍👍
making your own soft using what you’ve learned.
You are welcome from FPGA community :) Let me know if you would collab stream :)
CAN YOU SUBMIT THE SOURCE FILES?
According to the UG470 (page 22), PUDC_B should be tied to VCCO14 or ground directly or via resistor with 1k or less. 4k7 is too much.
🙂🙏
The worst tNice tutorialng soone can do after starting is quitting... never give up and the rewards will be greatly appreciated