9.1. VHDL design philosophy

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Writing VHDL can be very simple. In fact it can be too simple. But writing good VHDL depends on understanding some foundational philosophies about what it is and what it is trying to represent.

[@gvcallen]

Not sure how I discovered this channel but your introduction was pin-point for me (an EE graduate with no FPGA knowledge). Thanks!

[@ranveerdhawan744]

Sir please try adding a playlist for Verilog and TCL also