FPGA and DSP ep. 1:Efficient parallel FIR filter implementation on FPGA

#FPGA #DSP #Xilinx #FIR
Description
Implementing an efficient parallel FIR filter in VHDL.
The implementation is aimed at the Xilinx 7 families.
References
[1]Xilinx, “UG479 7 Series DSP48E1 Slice”
[2] Udo Zӧlzer, ”1.3.3 Digital systems” in DAFX: Digital Audio Effects
[3] R.Woods, J.McAllister ,G.Lightbody, “8.4 Pipelining DSP System ” in FPGA-based Implementation of Signal Processing Systems
[4] Richard G. Lyons, “ 13.24 Improving Traditional CIC Filters” in Understanding Digital Signal Processing
[5]Xilinx, “DSP48E1 Switching Characteristics ” in Zynq‐7000 SoC : DC and AC Switching Characteristics
Sources
Filter code: github.com/DHM...
Coefficient translator: github.com/DHM...