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Best explanation of a process that I have ever encountered.👍

th-cam.com/video/kxG83utFFDc/w-d-xo.html is AB.

I believe the label is necessary for instantiating because I am literally unable to instantiate components without labels. It gives me errors.

i dont usually comment but slutty explanation merci mon ami

so in your example function, if I want to take care of both dynamic hazard and static hazard (0->1->0 and 1->0->1) I need to multiply the specific problematic term in F like you said to fix the dynamic hazard (let's denote it now as F_tilde) and in addition I need to multiply F_tilde with the term that fix the 0 static hazard and then add the term that fix the 1 static hazard? so all in all we will get that F_fixed = F_tilde * (0 static hazard fix term) + (1 static hazard fix term)?

He just starts to introduce a Wallace Tree multiplier and immediately make two 'improvements.' It just adds confusion. Should stick to a simple example first, then note the improvements.

Hello There, Thank you for the explanation Sir. I am having a bit of an issue while simulating the Read Mode of a 6T SRAM Cell. So, I can successfully write the value into the Cell and check if they are retained when I put the Cell in Standby Mode (WL = 0). However, For the Read Mode, what I do is I pass Pulse signal of VDD to both BL and BL' for about 1.5 microseconds and then keep it low. Then, I try to turn on the WL at 2 microseconds but what ends up happening is that both Q and Q' values are same which oscillate between 0.268 and 0.832 V. So, Should I actually Use Capacitors in the Circuit when using Read Mode so that the Capacitors can be pre-charged?

Helpfull

thank you so much for the video. now i can fully understand the method.

One of the best lectures on metastability or probably the best explanation.

How to become a layout engineer

Very beautifully explained. Thanks for posting the videos professor.

Incredible videos, thank you so much. So well structured and easy to understand!

Thank you for your video. I always found it boring when I needed to read an explanation about the Wallace tree before. Therefore, I gave up before making an understanding of it.

whats the use of encoder and decoder, why do we use it?

whats the difference between asynchronous and sysnchrounos?

Very useful series. Thank you so much. It is helpful for my career

best and clearest explanation. I wish I knew that when I started with circuit design. It's so clear on point. Than you sir.

For the predecoder, if there is AND gate available, could we replace NAND+Inverter to AND, what's the pros and cons?

Simple and precise!

thankyou so much, great video

Hi, is cc'+c' or c'(c+c') also represents dynamic hazard like cc'+c or c(c+c')?

Awesome video! Really thoroughly explained and I definitely learned a lot

Not sure how I discovered this channel but your introduction was pin-point for me (an EE graduate with no FPGA knowledge). Thanks!

thanks for your effort Dr. Karim Abbas 👍

thank you very much. helped a lot

Your content is simple and fantastic! a lot of people are missing this out!

Couple questions. * When computing the setup and CQ times, shouldn't we take into account the charging time of the capacitor? Or is this implicitly part of the tI's and tT's? * At 9:21 you mention that the requirements on the 1--1 and 0--0 overlap are more stringent than in static CMOS, and hence racing is more of an issue. But is it really that stringent? Roughly speaking, you'd think that the overlap time is roughly the delay time tI of a single inverter, right? * In the series of RC's in 10:54 onwards, why are they all connected? Wouldn't the transmission gates be closed alternatingly?

Thank you for the wonderful lectures. I have a question about the cascaded network in 4:28 onwards. The PUN appear to receive an inverter clock signal. But would it not have been simpler to simply swap the tail nMOS and the head pMOS for a pMOS and nMOS respectively, and just give it an un-inverted clk?

great video!!!

excellent tutorials , thank-you

Great explaination sir..This 7 minute video made me subscribe ur channel

Nice explanation | Helpful information ... Ty

i love you sir

Nicely explained👍🏻

hai?? baigan

Really great explanation. Thank you!

at 7:22, it seems that DL value will be <=1, but earlier it was told that DL is measured in ppm. How are these two things related ??

Sir, is there any open source student version eda tool to work upon this dft domain?

Thanks for the refresher. It is interesting to note that the final circuit was essentially a mux. Which if you are using a mux for clocking, latch en, or set/clr that you have a potentially for glitches on that line.

Content is superb but there is a hell lot of advertisement, in every 3 mins one ad will appear...!!!

You have a mistake, sir. You did not consider the Carry-overs. This is all wrong.

Good work ✅

Shouldn't the fault coverage be 2500/3000 in this example instead of 500/3000?

I found a Gem 💎

جزاك الله خيرا وجعله في ميزانك و وفقك في حياتك يا رب \شرح وافي جدا جدا وجميل فعلا

WOW Karim you are great thanks alot

why 2*Vtn instead of Vtn in case of Clock =1 and Vin =1...?

why do we have inverted gate?

Amazing explanation of the benefits and costs for using SCAN Registers.