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Electron Tube
เข้าร่วมเมื่อ 20 มี.ค. 2019
www.electrontube.co
Everything digital electronics. Each playlist is a standalone module approaching an independent topic. Each video covers a specific point.
Everything digital electronics. Each playlist is a standalone module approaching an independent topic. Each video covers a specific point.
14.25. Lifetime of a chip
The reliability of microchips goes in phases. Behavior in early life is substantially different from that in useful life, and the wear out stage indicates the product is exiting the market. Understanding the features of each phase is important to the management of design goals.
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14.24. Reliability of VLSI systems
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Reliability is at once related to and distinct from testing. Reliability reflects on the behavior of a system or component over time. It is related to defects that accumulate or worsen over time. Some measure of unreliability is inevitable in VLSI.
14.23. Finding and solving dynamic hazards
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Dynamic hazards can be detected and solved from equations in a very similar way to static hazards. However, the entanglement of static and dynamic hazards must be approached very carefully because you might miss inadvertently miss some glitches.
14.22. Anatomy of dynamic hazards
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Dynamic hazards are much harder to discover and deal with than static hazards. However, once we realize that dynamic hazards are essentially transitions with an embedded static hazard, things start to get much better.
14.21. Static hazards in complex circuits
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We take a deeper look at how complicated logic circuits can be made glitch free. This requires a good understanding of how equations translate into differential paths through the circuit.
14.20. Static hazards in logic equations
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Using Karnaugh maps or logic circuits to detect and solve static hazards is not a scalable approach. As the number of input variables increase, K-maps become untenable. Fortunately, there are very easy ways to detect the possibility of glitches straight from logic equations.
14.19. Static-0 hazards
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Static-0 hazards are very similar to static-1 hazards. They come from very similar sources and are solved in very similar ways. However, because the stable zero at the output is a result of an AND gate instead of an OR gate, we must approach the problem a little differently.
14.18. Static-1 hazards
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Static-1 hazards occur when you expect the output of a circuit to remain stable at '1', but it temporarily glitches down to zero. This occurs due to differential delay through the circuit and is easily visible from Karnaugh maps.
14.17. Glitches and logical hazards
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Glitches are unexpected peaks and dips in logic outputs from combinational circuits. We would normally not care about the appearance of these glitches in synchronous pipelines, but in latch loops and asynchronous circuits they can be devastating.
14.16. Boundary scan & JTAG
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The boundary scan technique allows us to probe pins of chips connected to PCBs. The standard used to manage boundary scan is called JTAG. While boundary scan is mainly used to test copper tracks and soldering connections on PCBs, it can be combined with other DFT techniques to test individual chips.
14.15. PCB design & fabrication
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Printed Circuit Boards are used to combine multiple ICs with passive components to form a bigger system. The design and fabrication of PCBs has a lot of parallels to the design and fabrication of microchips, albeit much simpler and at much larger dimensions.
14.14. IC package types
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There are many IC package types to choose from. However, finding one that fits exactly to the needs of your die isn't always simple. There is always a tradeoff between simplicity and the number of pins you need, making it even more imperative that you have good pin economy.
14.13. IC packaging
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When you buy a microchip, it does not come as an exposed die. It comes in a tight little plastic container. This is the IC package, and for something so seemingly simple, we certainly expect it to do a whole lot of things.
14.12. Testing memories: coupling & NPSF
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Simple fault models like the stuck at fault model are a good starting point for representing memory faults. However, realistic models are significantly complicated by the fact that most memory faults involve interactions between multiple cells.
14.11. Testing memories: stuck at & transition faults
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Memories are designed with fundamentally unique metrics in mind. Thus, testing memories has to be different from testing random logic. Memories have one thing going for them: they have to do something very simple to be functional: write and read a '0', and write and read a '1'. But that is where the simplicity ends.
14.9. Automatic Test Pattern Generation
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14.9. Automatic Test Pattern Generation
14.4. Yield, Defect Level, and Fault Coverage
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14.4. Yield, Defect Level, and Fault Coverage
Best explanation of a process that I have ever encountered.👍
th-cam.com/video/kxG83utFFDc/w-d-xo.html is AB.
I believe the label is necessary for instantiating because I am literally unable to instantiate components without labels. It gives me errors.
i dont usually comment but slutty explanation merci mon ami
so in your example function, if I want to take care of both dynamic hazard and static hazard (0->1->0 and 1->0->1) I need to multiply the specific problematic term in F like you said to fix the dynamic hazard (let's denote it now as F_tilde) and in addition I need to multiply F_tilde with the term that fix the 0 static hazard and then add the term that fix the 1 static hazard? so all in all we will get that F_fixed = F_tilde * (0 static hazard fix term) + (1 static hazard fix term)?
He just starts to introduce a Wallace Tree multiplier and immediately make two 'improvements.' It just adds confusion. Should stick to a simple example first, then note the improvements.
Hello There, Thank you for the explanation Sir. I am having a bit of an issue while simulating the Read Mode of a 6T SRAM Cell. So, I can successfully write the value into the Cell and check if they are retained when I put the Cell in Standby Mode (WL = 0). However, For the Read Mode, what I do is I pass Pulse signal of VDD to both BL and BL' for about 1.5 microseconds and then keep it low. Then, I try to turn on the WL at 2 microseconds but what ends up happening is that both Q and Q' values are same which oscillate between 0.268 and 0.832 V. So, Should I actually Use Capacitors in the Circuit when using Read Mode so that the Capacitors can be pre-charged?
Helpfull
thank you so much for the video. now i can fully understand the method.
One of the best lectures on metastability or probably the best explanation.
How to become a layout engineer
Very beautifully explained. Thanks for posting the videos professor.
Incredible videos, thank you so much. So well structured and easy to understand!
Thank you for your video. I always found it boring when I needed to read an explanation about the Wallace tree before. Therefore, I gave up before making an understanding of it.
whats the use of encoder and decoder, why do we use it?
whats the difference between asynchronous and sysnchrounos?
Very useful series. Thank you so much. It is helpful for my career
best and clearest explanation. I wish I knew that when I started with circuit design. It's so clear on point. Than you sir.
For the predecoder, if there is AND gate available, could we replace NAND+Inverter to AND, what's the pros and cons?
an AND is a NAND and an inverter - see the CMOS logic design
Simple and precise!
thankyou so much, great video
Hi, is cc'+c' or c'(c+c') also represents dynamic hazard like cc'+c or c(c+c')?
Awesome video! Really thoroughly explained and I definitely learned a lot
Not sure how I discovered this channel but your introduction was pin-point for me (an EE graduate with no FPGA knowledge). Thanks!
thanks for your effort Dr. Karim Abbas 👍
thank you very much. helped a lot
Your content is simple and fantastic! a lot of people are missing this out!
Couple questions. * When computing the setup and CQ times, shouldn't we take into account the charging time of the capacitor? Or is this implicitly part of the tI's and tT's? * At 9:21 you mention that the requirements on the 1--1 and 0--0 overlap are more stringent than in static CMOS, and hence racing is more of an issue. But is it really that stringent? Roughly speaking, you'd think that the overlap time is roughly the delay time tI of a single inverter, right? * In the series of RC's in 10:54 onwards, why are they all connected? Wouldn't the transmission gates be closed alternatingly?
Thank you for the wonderful lectures. I have a question about the cascaded network in 4:28 onwards. The PUN appear to receive an inverter clock signal. But would it not have been simpler to simply swap the tail nMOS and the head pMOS for a pMOS and nMOS respectively, and just give it an un-inverted clk?
great video!!!
excellent tutorials , thank-you
Great explaination sir..This 7 minute video made me subscribe ur channel
Nice explanation | Helpful information ... Ty
i love you sir
Nicely explained👍🏻
hai?? baigan
Really great explanation. Thank you!
at 7:22, it seems that DL value will be <=1, but earlier it was told that DL is measured in ppm. How are these two things related ??
Sir, is there any open source student version eda tool to work upon this dft domain?
Thanks for the refresher. It is interesting to note that the final circuit was essentially a mux. Which if you are using a mux for clocking, latch en, or set/clr that you have a potentially for glitches on that line.
Content is superb but there is a hell lot of advertisement, in every 3 mins one ad will appear...!!!
use add blocker
You have a mistake, sir. You did not consider the Carry-overs. This is all wrong.
Good work ✅
Shouldn't the fault coverage be 2500/3000 in this example instead of 500/3000?
I am having the same doubt, formula says uncovered/faults but he did covered/faults , it should be 2500/3000 right??
I found a Gem 💎
جزاك الله خيرا وجعله في ميزانك و وفقك في حياتك يا رب \شرح وافي جدا جدا وجميل فعلا
WOW Karim you are great thanks alot
why 2*Vtn instead of Vtn in case of Clock =1 and Vin =1...?
why do we have inverted gate?
Amazing explanation of the benefits and costs for using SCAN Registers.