VHDL Lecture 21 Lab 7 - Voting Machine Explanation

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[@conorstewart2214]

I know this is a relatively old video but it is worth pointing out that this design can be simplified because the check and done states are unnecessary and that one hot assignment also uses more resources than other methods but they can get complicated with figuring out the optimal configuration, but I do get that this is easier to explain and it has been a great video series so far.
edit: If you think about it the initial state is unnecessary as well.

[@amrutamali7269]

Hi. I have followed all the steps but could not synthesize the code as getting WARNING:Xst:2677 - Node of sequential type is unconnected in block . Could you please help me to resolve this?

[@EDUVANCE]

There might be an assignment in your code you may have missed. Also even if a warning is generated, the code should be synthesized. Check if you have anything mentioned in errors list.

[@coolwinder]

Why does Finite State Machine needs to be clocked? Can't we build sequential circuit for FSM? Thank you.

[@EDUVANCE]

Finite State Machine Design is a combination of combinational and sequential logic. The presence of clock is required to transition from current state to next state on a particular clock edge.