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- เผยแพร่เมื่อ 4 เม.ย. 2016
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See how the Go Board can communicate with the computer. Learn about how a UART works. UARTs are easy ways to transmit and receive data between the computer and the Go Board. This project builds a receiver. The next project builds a transmitter. This is a fun one!
VHDL Simulation Environment (EDA Playground):
www.edaplayground.com/x/5vEh
Verilog Simulation Environment (EDA Playground):
www.edaplayground.com/x/4Lyz
Tera Term Download:
ttssh2.osdn.jp/index.html.en
For the text version of this project (and full code):
www.nandland.com/goboard/uart...
Support this channel! Buy a Go Board, the best development board for beginners to FPGA:
www.nandland.com/goboard/intr...
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/ nandland - วิทยาศาสตร์และเทคโนโลยี
I really love the little go board as a chance to learn fpga stuff. And I appreciate all the work put into designing and making all these tutorials--twice!--to teach it.
But I have to say, I'm a little enraged at this one. "We are building just a receiver. Give it a shot!" I struggle for 2 hours trying to come up with a way to build a receiver that doesn't involve building a transmitter to send to it and finally unpause the video. "Threw together a quick testbench (which btw is a transmitter)". Oh and it uses tasks, which have never been even mentioned. And for loops, which have been explicitly forbidden.
There's also no scaffolding here. It's just...here's the owl. How would I go about building this a piece at a time?
A very nice way of presenting. Definitely your work is very helpful for new comers into ASIC/FPGA Field. You are doing great work. Please keep it UP.
explanation is good and code is also simple and enable to understand
Really awesome resource. Thank you
Great tutorial, thank you!
Future video request, something covering external RAM interfacing.
you are doing god's work son
Dude, thank u very much u were very helpful
Well done!
Thanks you very much sir.
Thanks for the great explanations and easy to understand code! Just one quick question. What happens if we don't receive a correct stop bit? Like for whatever reason, the next bit after the MSB data bit would be 0, then what happens? I guess we should just empty whatever we received, not trigger the valid bit and proceed to the cleanup state right?
very helpful. cheers
Hi do you have any verilog examples of an even parity bit before the stop bit. I'm struggling trying to implement it.
Hey nandland, it's a great tutorial. I just have one doubt. What is the input to I_rx_serial for the go board. How did you assign the pins for it?... I am trying to implement it in zedboard and confused with the input part. It would be helpful if you could share it. Thanks once again!
Hi, I tried to run the code of yours in Vivado 2015.3 and when I checked the (r_Clock_Count) value using "$display" statement for StartBit detection, it counted till "22' and after that simulation was finished but in fact It should have counted till "114" and then go to next state of Sending Data Bits. Could you please explain the reason for this?
I personally think there should have been two separate playlists - one for verilog, and a different one for VHDL. It isn't user friendly to expect the watcher to skip through the parts we don't care about on every video. I really appreciate the content though!!
Hello sir if possible kindly give me the information regarding the schematic diagram explanation of UART receiver and transmitter... I'm unable to understand this thing sir...
Thank you
Thanks
23:11
For anyone who just wants the VHDL part
Great video!
You could also make the "CLKS_PER_BIT" an input instead of a parameter to make the design more flexible, so you can support different baud rates without making new designs with different parameter value each time.
Parameters can be overridden at compile time. Check out this simulation here where I do exactly that: www.edaplayground.com/x/4Lyz
Parameters are better than inputs because they can determine things like bit-widths, which cannot be a dynamic input or the tools will complain.
But yes, if you want to change your baud rate dynamically, it would have to be an input, perhaps that's what you're getting at?
Yes, parameters are great :)
I meant specifically change the "CLKS_PER_BIT" parameter to an input to get different baud rates during run time, without compiling the design.
Vhdl section at 23:00
Did this on Basys 3. Was overflowing 8 bit register and took me forever to find.
Did you check the State Diagram generated by Quartus? There is no transition from s_RX_Data_Bits to s_RX_Stop_Bit. Any idea why is it like this?
Is it possible to use the logic behind this code for a serdes implementation?
Sir,i cant't understand the schematic diagram kindly explain this problem.
Thank you
great work can you please send me the state diagram and state table of the fsm
Can you please Explain the Test Bench?
1. I know how we calculate g_CLKS_PER_BIT. But could you please tell me what is the purpose of using it? Why do we use it?
2. Usually, a bit period is calculated as 1/baud rate. How does g_CLKS_PER_BIT define the bit period?
1. It makes the code more flexible and reusable. See more about generics: www.nandland.com/vhdl/examples/example-generic.html
2. 1/baud_rate is bit period, yes. CLKS_PER_BIT is how many clock cycles there are in a bit period. In our case, the Go Board has 25 MHz clock, which is 40 ns. If using 57600 baud, that's bit period of 17.36 us, so there are about 434 clock cycles in a bit period using those numbers.
why use a byte in particular? Could I define the maximum bit index as like 256? then I would get a 256 bit word from which I could sample four 64 bit words?
nice. when you show your board at the last minute, why there is not wire for i_RX input? i just see power cable there, thanks
wooah, so that black cable not just for power? but also for comunication? like arduino? im confused because in my fpga, we must wiring from rx port fpga to tx max3232 and convert to usb
Nope! It's for power, programming, and communication with the FPGA. Pretty sweet huh?
speechless XD thanks for the very usefull information!
Hello all, unfortunately Synthesis failed with the following error message: "Slice range direction does not match argument range". Further investigation shows that this line is the error cause: "i_Binary_Num => w_RX_Byte(7 downto 4)". Does anybody why? THX and BR Marco
I am using the yosys tools and your go board and made it to this project before I got stuck. I have looked at the yosys documentation and can only determine that the output was optimized out of the design before I got to the final step. Can you possible provide a script that would show the right options to use with yosys and arachne-pnr?
Hm, my guess is that the signal name on the Pin Constraints file does not match the signal name in your Verilog code. Make sure the signals match exactly including capitalization. Also double-check that the signals are in the Pin Constraints file and going to the right pin.
Turns out my serial port program had hardware flow control turned on. Turned that off and it now works just fine. Thanks for helping.
Midi Physical Layer: (for synths keyboard drummachines sequencers controllers...)
0mA=logical 1 (midi works with current swing, instead of rs232 voltage swing)
5mA=logical 0
31250 Baud +-1%
25Mhz 25 000 000/31250 = 800 Clocks per Cycle (to sample middle of bit)
2uS max Rise/Fall Time
No Handshake
No Parity
hope that i can modify your vhdl code to get a midi receiver (extremly newbee i am)
Thank you so much. With your help I have successfully implemented uart receive on my spartan 6 fpga. Can you please help me how to recieve multiple bytes of unknown length and a control signals goes high when all bytes are received?
did you write something down for multiple bytes. I need the same thing.
can you explain what is c_BIT_PERIOD here?? and what is the significance of it?
Hey, these tutorials are excellent. However, your safe locking mechanism state machine has some serious security issues. I'm glad that you are putting so much time and effort into making FPGA programming accessible, keep doing that and definitely do not go into safe/lock design.
Thanks for the comment, can you elaborate?
I'm just joking really, but if you used that state machine for a real safe, and it had any indication that you entered a digit incorrectly, you could crack the safe by pressing each button and remembering which one didn't cause it to do back to the idle state, in a short time you could figure out what the real pass-code was. If there was no indication of an incorrect pass-code, then you would still have an issue because any incorrect digit starts over at the idle state, so the two consecutive pass-codes 1-2-4 and 7-9 would still open the safe, even though neither is the correct pass-code. I imagine (without thinking it through too much) that this could be leveraged to make brute forcing the pass-code happen much faster.
Okay yes, I do NOT recommend my super simple example for creating a real safe, hahaha.
Hey man, would you please help me with the constraints? I'm working on a Zynq7000, and I can't seem to access the Tx and Rx pins easily. I'm really confused :(
Did you get any help for your question?
i dont know the meaning of this line ,if (r_Clock_Count < CLKS_PER_BIT-1) in Rx_Data
please explain
The purpose is to count up one entire bit length. CLKS_PER_BIT is a parameter so the design is more flexible, but it's just a number that the counter counts up to. That represents one entire bit period of the UART receiver. Make a bit more sense?
can I get the code for this? both design and tb please
How did this code work without adding "library work;" on top? I copied the code on vivado xilinx (in vhdl) to check but there's an error. Says "binary_to_7segment is not compiled in xil_delaultlib". All errors were on lines that included "work.binary_to_7segment" phrase. Does anyone know how to solve this?
Yeah that's a Xilinx thing. It was compiled for a Lattice FPGA.
4:02 aren't RS232 and UART different things?
where exactly is o_RX_DV pulse going and why is it important?
It's going out of the module to anyone who needs it. It's an important signal. Without a Data Valid (DV) pulse, when would you know when the received data is valid? The received data will be changing and any module that uses this data needs to know when to "look at" the data signal. Data Valid pulses are extremely useful for this. You'll notice that I use them all the time.
He seems to check when the start bit is received but in the code I do not see him check for when the stop bit is received. Does anyone have an explanation for this?
I am wondering that as well.
He had a typo for a comment on the VHDL receiver portion related to the transmitter. It may just be a copy and paste error, where he wrote the transmitter modules first and converted them to receiver modules.
awsome tutorial. can i put the w_rx_byte direct to output? without 7seg. are the data will latch? i use xilinx mercury spartan 3a, it dont have develpoment kit and 7seg, so i just put the w_rx_signal direct to output in pin GPIO 0 - 7 and connect to 8 led. i followed your step, but when i pres number 1 on my keyboard, my led blink fast, instead of the led must be forming to 31 (00110001) In ascii
sory for my bad english XD
Good question, it should register it and keep the value, but give it a try to make sure. As far as the LEDs blinking fast, I'm not sure what's causing that, but it sounds like you should be registering your output to your LEDs and only updating the value when a new byte is received. For that I recommend using w_RX_DV (Data Valid). That pulse should tell the LEDs to change, otherwise they should maintain their old value.
i did, but the result is same. sory can i see your binary_to_7segment.vhd? i just want to check your full code, if there is still wrong, so the problem is from my hardware. sorry for asking too much, i am new at fpga, i just start studying this stuff from 2 weeks ago haha
No problem. Everyone needs to start somewhere, and starting something new is always the hardest part. Stick with it and it will start to make sense. Here's the binary to 7 segment code: www.nandland.com/vhdl/modules/binary-to-7-segment.html
so great!!!! thank you!! but can i see your ucf code for this project, please??
www.nandland.com/goboard/Go_Board_Constraints.pcf
thank you very much from indonesia!
The code is on eda playground and not website. Easy to miss.
Code isn't working in vivado 😢
How to insert the start and stop bit while we sending data from Tera Term?
Only stop bits are able to be modified. But they're automatically inserted into the datastream by the program.
Thank you very much for the reply. Can you indicate me in the code where start bit (logic 0) has been inserted.
want to know why to use c_BIT_PERIOD??.how it is calculated..
Check out the code comments:
-- Want to interface to 115200 baud UART
-- 25000000 / 115200 = 217 Clocks Per Bit.
constant c_CLKS_PER_BIT : integer := 217;
Take your input clock rate (25 MHz) and divide by the UART Frequency (115200 baud) and you get the number of clocks per bit.
What is the use of RX serial bit???
ignore this comment
how did u calculate c_CLOCK_PERIOD_NS and c_BIT_PERIOD
Clock period in nanoseconds relates to the operating frequency of the FPGA. The go board uses a 25 MHz clock, which has a clock period of 40 ns. Bit Period relates to the UART bit period. It determined the baud rate (bits per second) of the UART.
In the testbench we have bit period as 8600.. but a baud of 115200... can you please explain more about the bit period
1/115200 = 8680 nanoseconds. It's just to simulate the 115200 bits per second period (~8600 nano seconds) for the testbench.
nandland thank you so much.. btw I was working on this project and compiling on xilinx ise design suite. But for some reason the r_rx_serial is not toggling hence I am not getting any output. Any possible reasons
@@Nandland clock bit period is 8600. It depends on baud rate only. 1/ baudrate (in nanoseconds). It does not depend on frequency of fpga ?
SIR.HOW TO GIVE INPUTS PLEASE EXPLAIN THAT
Connect the Go Board to your computer. Open up a COM port using a program like Tera Term. Type keys on your keyboard.
i don't see why parameter c_CLOCK_PERIOD_NS = 40; and parameter c_BIT_PERIOD = 8600; in the test bench
If it's the test bench, it's probably because I just wanted to speed up the simulation time. Keeping the "real" numbers in there cause the simulation to take a really lonnnnnng time.
thank you
why is this clocked if UART is assynchronous?
We need to bring the asynchronous interface into our synchronous world.
@@Nandland but then how is uart more assynchronous than spi or i2c? Thanks for the reply!