This was absolutely not the content I was searching for but I have no regret having listened to every seemingly wise word you just said. Thanks a lot !
I *SO* concur with your uniform ground approach in all mixed technology cases except where there are specific reasons. Split grounds and net-ties are a nightmare to get right and in my experience cause FAR more EMC issues than they avoid. Proper circuit and trace segregation is definitely the way to go, and is why careful component placement is such a key step before going anywhere near a routing tool. And with things like switching regulators, I keep the close-coupled, high current paths as short and wide as possible on the component layer, (another trick to perform during placement), keeping trace impedance minimised and avoiding vias in those paths at all costs. Once power rails have been sufficiently decoupled on the component side, I then route the rail to a split power plane or a trace network as the design requires. Keeps EMC controlled, improves performance and aids thermal management. What’s not to like?
Hey Zach! I'm used to answering my questions, but now I can't keep up with you since you answer my questions without asking them :)) thanks a lot for the video
Absolutely agree that you should never split your PGND/DGND/AGND (aka 0V), otherwise you are asking for trouble when you go through EMC/EMI testing If you are worried about signal noise then segregate your circuits, as in move the power supply to one corner of the board, the digital section to another, and the analog section to another again. Then when you transition from one EM zone to another (say analog to digital), you add some inline filters at the EM zone boundary
Others have touched on this but, in buck converters, I think it's worth emphasising that the distinction between different grounds is less important than understanding where the principal high current loops are and ensuring that they are as small, as low impedance as possible and preferably on the component layer only. The inductance of the return current path (ie "GND") is make-or-break, both functionally and in terms of noise caused by common impedance coupling [in ground currents]. Here, both critical current paths involve the negative plate (ie ground) of both the input and output capacitors. When the switch is on, current flows from the positive of the input caps, out through the switch and inductor¹, and into the output caps' positive, returning _from the output caps' GND back to the input caps' GND._ When the switch is off, current flows from the inductor¹ and output caps' positive, returning back _into the output caps' GND and the inductor through the diode_ (which is more usually a FET). There is a third current loop through the input capacitors as they are recharged by the source supply. These large switching return currents should not be common with load currents in the ground plane if at all possible and, instead, stay on the the component layer. This is, effectively, a separate ground. TI datasheets usually recommended a layout which has these return current paths go through the ground plane below the buck converter. That will work and not cause problems in an evaluation board but it is not optimal in an application board, especially when the buck converter(s) can't be well isolated by sectioning the board, because the parasitic partial inductance of the vias to the ground plane together with the parasitic partial inductance of the plane itself contribute to common impedance which produces noise voltages in proportion to the magnitude of the switching current. Those noise voltages can then couple into any application circuit that shares a common return current path, ie the ground plane. [Ed:] That said, there is an argument for sending return currents in the plane below rather than on the component layer, which says that because the magnetic field from the forward current is opposite to that from the return current, the magnetic fields cancel thus reducing EMI. Two problems with this: 1. it only works if the return current follows (in the ground plane) exactly the path on the component layer, but what path return current follows through a solid ground plane is frequency dependent, and 2. switching return currents still disturb application circuits with noise arising from common impedance in the ground plane. ¹ This is DC, so current always flows in the same direction. However, current in the inductor increases (dI/dt is positive)² as it charges when the switch is on, and decreases (dI/dt is negative - but still flowing in the same direction)³ as it discharges when the switch is off. ² Inductor potential is always opposite to (and in proportion to) the _rate of change of current_ as it charges, so the potential across the inductor is negative - ie subtracts from the source voltage - which is how the buck converter steps-down voltage presented to the load. ³ The potential across the inductor is now positive as it discharges so, together with the output capacitors, it acts as a current source for the load. The voltage seen by the load is determined by the charge in the output capacitors, `Vout=Qout÷Cout`. The voltage ripple, then, is determined by the size of Cout, the load current and the switching frequency.
I had a project where I had multiple type of GNDs (SBC GND, MGND, AGND, DGND, OSCGND etc) but eventually they were all connected together to the main GND using - as we call it - a starpoint (something like a "net tie"). 6L board. On one of the layers was the split and connection multiple GNDs, on another one a complete GND fill.
At that point you basically just have 1 oddly shaped ground conductor. No problem with that as long as you route over it correctly (only over ground). Rick Hartley will disagree with me until I start showing him some strange board shapes and draw out the area where routing is confined.
Awesome video, thanks for the content. Good rule of thumb to implement split planes for low frequency applications. Also to add that for large current applications this becomes quite important. Example I keep the return paths for a motor driver completely isolated from my ground and use net ties to avoid introducing offsets when my motor is running which can be quite large.
You can have as many "Ground" nodes as you want below 100 KHz. But to pass EMC / EMI requirements you only get one RF ground above 100 KHz. You pass EMC / EMI by designing controlled impedance transmission lines for each and every signal that has intended or unintended content above 100 KHz. Splitting or cutting up ground reference layers are the single most common cause if EMC and EMI failures. You keep noise current out of sensitive signals by designing the transmission lines, not by cutting up your RF ground.
it does not only depend on the frequency, it depends on the rise / fall times. Current ICs have rise / fall times of pico sec and can cause emi / emc problems EVEN at low frequencies. There are interesting notes from Eric Bogatin and Rick Hartley on this.
@@cvillf4694 To make any AC signal requires frequencies. For a pure tone there is only one required. For a digital signal made up of rising and falling edges there are many frequencies spaced at the period of the signal. The fidelity of the transport of these signals depends on the amplitude and phase delay distortion of each of these signal components at all of the various frequencies.
Well, he explains in the video that high speed transmission lines have a well defined reference path that follows the trace closely. Additionally, he also said that split ground planes can be implemented properly and is preferable when the analog signals are low frequency. So your information doesn't contradict what was presented in the video.
@Plissken The key here is the "how" part of doing that properly. Most people don't do it properly and they try to do it when it is not needed. Audio is one example, but part of the reason for that is that sometimes your audio system will be galvanically isolated from your codec and speaker or transformer driver/amplifier, so you're forced to split things. Another instance if when your signals are very low level, like SNR ~ 1, in which case you also need to maintain isolation. You could do it with a galvanically isolated ADC, very tightly coupled transformer, or an optocoupler all with a very tight loop into your ADC. Similar idea going in reverse from a DAC.
How about ground for an audio codec like the AD1937? I did it with a separated ground and only routed digital lines over the dgnd and had an optional net tie with a junper, close to a 2x4 pinsocket which had the AGND and DGND nets connected with nice thick traces to their respective copper pours. I still had analog output garbage that could have been caused by EMI. Unfortunately I don't have equipment to measure EMI. I only have a kind of decent scope and an average multimeter. Maybe I'm just biting off more than I can chew here though 😅
Instead of using a net tie I used a zero-ohm resistor to connect PGND and AGND. I think that it is the similar way to do grounding in a dc-dc non-isolated converter.
Yes net tie and zero-ohm resistor are the same in this case for non-isolated converters. I think a zero-ohm resistor is simpler for routing just because you now do not need to create a specific net time component and the system will automatically separate the nets by name.
Thanks for the informative video. But i have two questions: In power converter, why should we connect the SGND and PGND? ( And in ADC why should we connect DGND and AGND with a tie?
In power converters with a primary ground (PGND) and secondary ground (SGND), these are isolated converters and you leave the grounds disconnected to maintain complete galvanic isolation. You can connect them if you want but you will eliminate the galvanic isolation, so it defeats the purpose of using an isolated converter. In ADCs, the AGND and DGND pins are already connected inside the package, so they do not have galvanic isolation. The main reasons to use a plane for connecting the pins are to confine noise from the digital I/Os away from the analog interface but without interrupting the ability to route everywhere else in the PCB. Using a net tie in the way you describe can make routing more difficult and it interferes with the return path from the digital section which creates greater radiated EMI and greater EMI susceptibility. So just use a ground plane, it is better for EMI/EMC and ease of routing.
i want to suggest you , maybe it will be more helpful if you show the effect of separated gnd with animation or Simulation , to understand what will be actually happened to separated gnd in facing with noise , this is somthing that literally confused us in Connecting GNDs Together and the location of this connection .
Hello Zach great video! So what about mixed signal PCB with 6 ADC, 3 of then on main PCB and rest of then on secondary PCB connected through connector. I need split GND and AGND on both PCBs so where I have to connect grounds together?
Great question I'd say it depends if you have isolated communication, or/and power and differential analog or digital signalling, but in the most cases, it'd be better to connect both grounds together. When deciding what you should do you must look at the return currents of your circuits elements/subcircuits, if you can imagine all of them, I'm sure you can decide what's the best solution for your circuit.
What sample frequency do the ADCs run at/what frequency is the signal you are sampling? Is the reference voltage for the signal you are sampling the same for all 6 ADC? The most sensitive signal is probably the one you are sampling? Do you need to pass EMC (is this a product or a hobby?)
Never ever use split grounds if you do not need isolation. Look at Rick Hartley's and Eric Bogatins video's. They have a joke at the EMI test houses. 'What kind of people use split grounds?... A customer.' th-cam.com/video/ySuUZEjARPY/w-d-xo.html
@@breedj1 unless the frequency of the signal in the analog part of the circuit is low, like audio frequencies. The return currents for such low frequency signals spread far and wide, they do not stick to the signal path. If they spread so as to be close to your fast digital signals then you will get noise in the analog section. How much? It depends 😜. But if you are sensitive to microvolts then very likely you will have to prevent the analog return paths straying into the digital area and the only way to do that is to separate them.
@@robiniddon7582 Have a look at the video it is very interesting. It shows that at around 2kHz the return currents are already taking the path below the trace. There is no benefit in using separate ground planes.
Common mode noise/interference is the enemy. The amount of noise/interference coupled into your PCB by signal and power supply wiring (antennas) will often swamp the amount of noise/interference coupling on the PCB itself. Use ferrite beads liberally.
I understand you need common mode chokes in the input of the circuit to deal with common mode noise. Ferrite beads would work for differential mode noise.
How about for a battery source (floating) with high DC voltage output using a transformer like the xenon flash capacitor charger like the LT3751? Their reference design on the datasheet shows a separate analog and digital ground areas on both the schematic and pcb drawings. I've read your blog post about the different grounding options for PSU but I'm not sure how to implement it on a battery source. Since I don't have an earth / chassis connection, would it still be ok or not, to connect the xformer primary ground with the secondary ground using Y capacitor to decouple the HF noise back to the primary gnd? Or should I just separate the two ground areas completely?
The reason there is separate grounds on the LT3751 reference design is because that system is a flyback controller, which uses a transformer. While there is not necessarily a requirement to use separate grounds on each side of a transformer, one of the reasons you would use transformer is to implement galvanic isolation, and since you are using a high DC voltage source you want to have that galvanic isolation with two different grounds on each side. Since you don't have an earth/chassis connection it is still okay to do the connection with the Y capacitor, in fact I would recommend trying this and examining high-frequency emissions from the system. You have to be careful with leakage across that capacitor though. If you have high leakage then you might cause annoying shocks at any HMI element in the design (buttons or connectors), there are EMC standards that specify limits on this type of ESD through leakage.
thanks, it is unclear for me tge last example, i couldn't notice the part where the onchip gnd is connected to PGND.. could you please clear it a bit, thanks
for that ADC example, even with a GHz Sample rate ADC, it would still be able to capture low frequency products. So anyway we need to split AGND and DGND right?
Is your SNR value near 1? Then maybe... If you are trying to measure a high frequency signal and you are worried about low frequency noise there are much better things you can do to measure the signal above noise without creating an EMI problem by splitting AGND and DGND. Splitting the GND net like that is a poor excuse for controlling noise when someone refuses to learn correct layout and routing practices. In addition, the GND pins on the ADC are connected internally! AGND and DGND splitting just makes the routing in the rest of the board more difficult.
@@Zachariah-Peterson thanks for your comment. I was not thinking straight. Actually for High speed ADC usually it can easily remove those low frequency by digital filter .
I think this video is VERY helpful to me as I am suffering some very serious ground noise inside my ADC board. I'm using FPGA to drive my AD9826 to receive voltage data and I use one single ground as the datasheet told me. But then I found the noise on the ground very high which interrupt the analog signal (in my case, the frequency of the analog signal is very low), do I need to seperate the ground and USE a piece of Ferrite bead to block the clock noise? And if the frequency of the input signal becomes higher (about serval MHz), what should I do to reduce the noise?
In the buck converter example, could we have one ground net for these two separate grounds (pins) but carefully layout the pulsed current part (SW node) away from the rest of the circuitry?
Sure you could, but the best strategy for SW node layout is with short connections. The reason is that the connections have their own loop inductance that can generate or receive EMI. That loop inductance is usually something like 5 nH/inch.
It's not a strict requirement. Technically because the PGND and GND pins are being connected with a piece of copper, they will have the same ground potential. The reason this is sometimes done is to control return currents in the plane layer; it enforces some isolation from nearby currents so that they do not interfere with the voltage measurement in the feedback line, and we would like for the feedback line to be either noise free or to only reflect the noise on the power bus in order to provide compensation through the converter's feedback loop. If the insulator layer is much thinner, then you can get away with using a complete piece of ground for your buck converter because any signals that might induce noise on that feedback line will have a more strongly confined distribution of their return current below the trace. It's equivalent to reducing crosstalk between the FB line and some other line.
I would say definitely not! The aim should be to keep grounds together in terms of voltage, and increasing the impedance between ground nets only encourages ground bounce between the nets. The best place for a pi-filter is connecting the supplies, between DGnd and AGnd, with the capacitor each side connected as close to the respective Gnd pin of the interfacing chip as possible.
No don't do this, it really is better all around to just use continuous ground unless you have a reason not to. @blue5375 mentions ground bounce between the planes, I think he is referring to the fact that the disconnected ground regions can have a potential difference (voltage) between them. The result is that if the potential between those regions starts oscillating, then you have a changing electric field between them that starts radiating, and you have basically created two big edge-coupled patch antennas. One reason to use different grouns is, for example, with use of an isolated ADC, which requires split grounds but the purpose is for galvanic isolation. I just finished a tutorial with this type of design, you can find the source files on my company website (search for Northwest Engineering Solutions and go to the Design Examples page under the Resources tab).
ugg, GND islands are such a disagreeable topic. As much as I know that return currents can be controlled in placement, I still prefer to carve out AGND separately then use a large Net tie. Once a signal from a sensor, that was on the regular GND, comes into a high impedance input of an op-amp, that's when I consider the signal now on and around AGND. I usually will place my net tie between DGND and AGND right under or around the ADC/DAC or Micro Controller and I'll route the analog signals around the AGND. Will you explain any holes in this logic? Not using this old school tried and true way is really hard to break, even when I know it can be done with proper placement and routing.
If you're only keeping the digital stuff in the digital area and the analog stuff in the analog area, and if you can guarantee the digital circuits are completed in the digital section and analog circuits complete in the analog section, then you've basically created an isolated system and the net tie becomes kind of meaningless. In some ways, the net tie is already meaningless because in a non-isolated ADCs the component links the GNDs on the die anyways, the exception is when the ADC is a galvanically isolated component. But with modern ADC packages or an MCU, you might have signals that must route over ground but they can't because of the split. I'm sure you could find some components where the interfaces are separated like you suggest but it is not always like that, just look at mixed signal ASICs or MCUs in quad packages. I think the biggest problem with the split AGND/DGND guideline is that newbies see it and they don't understand that they shouldn't route across the breaks in ground, but then they do it anyways. Then they wonder why they have excess radiation or fail susceptibility testing.
When talking about *where* to put the net tie around th-cam.com/video/19WnYPhNOH0/w-d-xo.html ... I missed the answer. As best I could tell, anywhere along the boundary should meet the 0V requirement in theory, and in practice, it seems you would want to be farther away from the chip, since that is something which could temporarily change that. A minute later, when talking about low-frequency analog signals that spread out, I would expect that you want the net tie to be as far as possible from those signals. But you suggested being near the chip, and relatively (given the boundaries) near the analog signal line ... what did I miss?
Actually I'm arguing that if you lay out the board properly then you don't need the net tie at all. If you look at these kinds of recommendations they will put it near the chip or directly under the chip. In the case where you can't control return paths or noise coupling, and then you start splitting GNDs, I think it's much better from a noise perspective to take an isolated design approach but that is much harder, now you have to worry about inductive or optical coulping across ground regions. If you do it wrong you'll have floating grounds that then radiate, it's a pain to do it correctly and it can make the rest of the layout harder.
@@Zachariah-Peterson So the real answer is that you should separate things by enough that you can do it as a single plane, and if you can't do that, try to isolate them completely, and if you can't do that, try to use a single net-tie, but you're already at 3rd-best, so worrying about *where* to put the net-tie is spending your optimization time on the wrong thing? And if you need a rule of thumb even for that, do whatever is conventional and won't make people curious, which often means "near the chip"?
@@jimjjewett If you're at the 3rd best solution then you've probably optimized the wrong stuff and put yourself in a corner where you're now forced to use a net tie instead of a single plane. At that point, might as well near do it the chip I and throw a wonky looking gap between your digital stuff and your analog stuff, but prepare yourself for excess noise!
This was absolutely not the content I was searching for but I have no regret having listened to every seemingly wise word you just said. Thanks a lot !
So glad you enjoyed it!
Jack sir absolutely correct where he also preferred solid ground plane for both AGND n DGND
I *SO* concur with your uniform ground approach in all mixed technology cases except where there are specific reasons. Split grounds and net-ties are a nightmare to get right and in my experience cause FAR more EMC issues than they avoid. Proper circuit and trace segregation is definitely the way to go, and is why careful component placement is such a key step before going anywhere near a routing tool. And with things like switching regulators, I keep the close-coupled, high current paths as short and wide as possible on the component layer, (another trick to perform during placement), keeping trace impedance minimised and avoiding vias in those paths at all costs. Once power rails have been sufficiently decoupled on the component side, I then route the rail to a split power plane or a trace network as the design requires. Keeps EMC controlled, improves performance and aids thermal management. What’s not to like?
Hey Zach! I'm used to answering my questions, but now I can't keep up with you since you answer my questions without asking them :))
thanks a lot for the video
Guys it really works, I checked
Absolutely agree that you should never split your PGND/DGND/AGND (aka 0V), otherwise you are asking for trouble when you go through EMC/EMI testing
If you are worried about signal noise then segregate your circuits, as in move the power supply to one corner of the board, the digital section to another, and the analog section to another again. Then when you transition from one EM zone to another (say analog to digital), you add some inline filters at the EM zone boundary
Im a student in electronics and communication engineering. Thanks for your advice, noted it down.
its there is any way to control the switching noise in PCB?
Others have touched on this but, in buck converters, I think it's worth emphasising that the distinction between different grounds is less important than understanding where the principal high current loops are and ensuring that they are as small, as low impedance as possible and preferably on the component layer only. The inductance of the return current path (ie "GND") is make-or-break, both functionally and in terms of noise caused by common impedance coupling [in ground currents].
Here, both critical current paths involve the negative plate (ie ground) of both the input and output capacitors.
When the switch is on, current flows from the positive of the input caps, out through the switch and inductor¹, and into the output caps' positive, returning _from the output caps' GND back to the input caps' GND._
When the switch is off, current flows from the inductor¹ and output caps' positive, returning back _into the output caps' GND and the inductor through the diode_ (which is more usually a FET). There is a third current loop through the input capacitors as they are recharged by the source supply.
These large switching return currents should not be common with load currents in the ground plane if at all possible and, instead, stay on the the component layer. This is, effectively, a separate ground. TI datasheets usually recommended a layout which has these return current paths go through the ground plane below the buck converter. That will work and not cause problems in an evaluation board but it is not optimal in an application board, especially when the buck converter(s) can't be well isolated by sectioning the board, because the parasitic partial inductance of the vias to the ground plane together with the parasitic partial inductance of the plane itself contribute to common impedance which produces noise voltages in proportion to the magnitude of the switching current. Those noise voltages can then couple into any application circuit that shares a common return current path, ie the ground plane.
[Ed:] That said, there is an argument for sending return currents in the plane below rather than on the component layer, which says that because the magnetic field from the forward current is opposite to that from the return current, the magnetic fields cancel thus reducing EMI. Two problems with this:
1. it only works if the return current follows (in the ground plane) exactly the path on the component layer, but what path return current follows through a solid ground plane is frequency dependent, and
2. switching return currents still disturb application circuits with noise arising from common impedance in the ground plane.
¹ This is DC, so current always flows in the same direction. However, current in the inductor increases (dI/dt is positive)² as it charges when the switch is on, and decreases (dI/dt is negative - but still flowing in the same direction)³ as it discharges when the switch is off.
² Inductor potential is always opposite to (and in proportion to) the _rate of change of current_ as it charges, so the potential across the inductor is negative - ie subtracts from the source voltage - which is how the buck converter steps-down voltage presented to the load.
³ The potential across the inductor is now positive as it discharges so, together with the output capacitors, it acts as a current source for the load. The voltage seen by the load is determined by the charge in the output capacitors, `Vout=Qout÷Cout`. The voltage ripple, then, is determined by the size of Cout, the load current and the switching frequency.
I had a project where I had multiple type of GNDs (SBC GND, MGND, AGND, DGND, OSCGND etc) but eventually they were all connected together to the main GND using - as we call it - a starpoint (something like a "net tie"). 6L board. On one of the layers was the split and connection multiple GNDs, on another one a complete GND fill.
At that point you basically just have 1 oddly shaped ground conductor. No problem with that as long as you route over it correctly (only over ground). Rick Hartley will disagree with me until I start showing him some strange board shapes and draw out the area where routing is confined.
Awesome video, thanks for the content. Good rule of thumb to implement split planes for low frequency applications. Also to add that for large current applications this becomes quite important. Example I keep the return paths for a motor driver completely isolated from my ground and use net ties to avoid introducing offsets when my motor is running which can be quite large.
Glad it was helpful!
You can have as many "Ground" nodes as you want below 100 KHz. But to pass EMC / EMI requirements you only get one RF ground above 100 KHz. You pass EMC / EMI by designing controlled impedance transmission lines for each and every signal that has intended or unintended content above 100 KHz. Splitting or cutting up ground reference layers are the single most common cause if EMC and EMI failures. You keep noise current out of sensitive signals by designing the transmission lines, not by cutting up your RF ground.
it does not only depend on the frequency, it depends on the rise / fall times. Current ICs have rise / fall times of pico sec and can cause emi / emc problems EVEN at low frequencies. There are interesting notes from Eric Bogatin and Rick Hartley on this.
I've said a variation of this in just about every video I've made on high-speed design and grounding, including this one
@@cvillf4694 To make any AC signal requires frequencies. For a pure tone there is only one required. For a digital signal made up of rising and falling edges there are many frequencies spaced at the period of the signal. The fidelity of the transport of these signals depends on the amplitude and phase delay distortion of each of these signal components at all of the various frequencies.
Well, he explains in the video that high speed transmission lines have a well defined reference path that follows the trace closely. Additionally, he also said that split ground planes can be implemented properly and is preferable when the analog signals are low frequency. So your information doesn't contradict what was presented in the video.
@Plissken The key here is the "how" part of doing that properly. Most people don't do it properly and they try to do it when it is not needed. Audio is one example, but part of the reason for that is that sometimes your audio system will be galvanically isolated from your codec and speaker or transformer driver/amplifier, so you're forced to split things. Another instance if when your signals are very low level, like SNR ~ 1, in which case you also need to maintain isolation. You could do it with a galvanically isolated ADC, very tightly coupled transformer, or an optocoupler all with a very tight loop into your ADC. Similar idea going in reverse from a DAC.
How about ground for an audio codec like the AD1937? I did it with a separated ground and only routed digital lines over the dgnd and had an optional net tie with a junper, close to a 2x4 pinsocket which had the AGND and DGND nets connected with nice thick traces to their respective copper pours. I still had analog output garbage that could have been caused by EMI. Unfortunately I don't have equipment to measure EMI. I only have a kind of decent scope and an average multimeter. Maybe I'm just biting off more than I can chew here though 😅
It worked! Tank you sir.
Glad it helped
Instead of using a net tie I used a zero-ohm resistor to connect PGND and AGND.
I think that it is the similar way to do grounding in a dc-dc non-isolated converter.
Yes net tie and zero-ohm resistor are the same in this case for non-isolated converters. I think a zero-ohm resistor is simpler for routing just because you now do not need to create a specific net time component and the system will automatically separate the nets by name.
Thanks for the informative video. But i have two questions:
In power converter, why should we connect the SGND and PGND? (
And in ADC why should we connect DGND and AGND with a tie?
In power converters with a primary ground (PGND) and secondary ground (SGND), these are isolated converters and you leave the grounds disconnected to maintain complete galvanic isolation. You can connect them if you want but you will eliminate the galvanic isolation, so it defeats the purpose of using an isolated converter.
In ADCs, the AGND and DGND pins are already connected inside the package, so they do not have galvanic isolation. The main reasons to use a plane for connecting the pins are to confine noise from the digital I/Os away from the analog interface but without interrupting the ability to route everywhere else in the PCB. Using a net tie in the way you describe can make routing more difficult and it interferes with the return path from the digital section which creates greater radiated EMI and greater EMI susceptibility. So just use a ground plane, it is better for EMI/EMC and ease of routing.
Really nice video to understand the concept about GND. Looking forward to your next video
Glad to hear that
Hello, thanks for your work! Can you make video about hatched polygon, about it's usage and benefits?
We recorded this and it is in editing now
i want to suggest you , maybe it will be more helpful if you show the effect of separated gnd with animation or Simulation , to understand what will be actually happened to separated gnd in facing with noise , this is somthing that literally confused us in Connecting GNDs Together and the location of this connection .
I believe I have shown some simple examples of this in other videos. But in any case I will see about creating an example, possibly in OpenEMS.
Hi, thanks for your video! I have a question, there are some circuits that has Field Ground. how can I layout that?
Hi
Can we use net tie for pcb with some high voltage blocks and some digital blocks???
Hello Zach great video! So what about mixed signal PCB with 6 ADC, 3 of then on main PCB and rest of then on secondary PCB connected through connector. I need split GND and AGND on both PCBs so where I have to connect grounds together?
Great question I'd say it depends if you have isolated communication, or/and power and differential analog or digital signalling, but in the most cases, it'd be better to connect both grounds together. When deciding what you should do you must look at the return currents of your circuits elements/subcircuits, if you can imagine all of them, I'm sure you can decide what's the best solution for your circuit.
What sample frequency do the ADCs run at/what frequency is the signal you are sampling?
Is the reference voltage for the signal you are sampling the same for all 6 ADC?
The most sensitive signal is probably the one you are sampling?
Do you need to pass EMC (is this a product or a hobby?)
Never ever use split grounds if you do not need isolation. Look at Rick Hartley's and Eric Bogatins video's.
They have a joke at the EMI test houses. 'What kind of people use split grounds?... A customer.'
th-cam.com/video/ySuUZEjARPY/w-d-xo.html
@@breedj1 unless the frequency of the signal in the analog part of the circuit is low, like audio frequencies. The return currents for such low frequency signals spread far and wide, they do not stick to the signal path. If they spread so as to be close to your fast digital signals then you will get noise in the analog section.
How much? It depends 😜. But if you are sensitive to microvolts then very likely you will have to prevent the analog return paths straying into the digital area and the only way to do that is to separate them.
@@robiniddon7582 Have a look at the video it is very interesting. It shows that at around 2kHz the return currents are already taking the path below the trace.
There is no benefit in using separate ground planes.
Good topic for beginners, great pick. :)
Glad you think so!
Common mode noise/interference is the enemy. The amount of noise/interference coupled into your PCB by signal and power supply wiring (antennas) will often swamp the amount of noise/interference coupling on the PCB itself. Use ferrite beads liberally.
I understand you need common mode chokes in the input of the circuit to deal with common mode noise. Ferrite beads would work for differential mode noise.
Awesome videos, easy to learn. It's easy to understand and why the gnd pcb design is really complicated haha
Glad you think so!
How about for a battery source (floating) with high DC voltage output using a transformer like the xenon flash capacitor charger like the LT3751? Their reference design on the datasheet shows a separate analog and digital ground areas on both the schematic and pcb drawings. I've read your blog post about the different grounding options for PSU but I'm not sure how to implement it on a battery source. Since I don't have an earth / chassis connection, would it still be ok or not, to connect the xformer primary ground with the secondary ground using Y capacitor to decouple the HF noise back to the primary gnd? Or should I just separate the two ground areas completely?
The reason there is separate grounds on the LT3751 reference design is because that system is a flyback controller, which uses a transformer. While there is not necessarily a requirement to use separate grounds on each side of a transformer, one of the reasons you would use transformer is to implement galvanic isolation, and since you are using a high DC voltage source you want to have that galvanic isolation with two different grounds on each side. Since you don't have an earth/chassis connection it is still okay to do the connection with the Y capacitor, in fact I would recommend trying this and examining high-frequency emissions from the system. You have to be careful with leakage across that capacitor though. If you have high leakage then you might cause annoying shocks at any HMI element in the design (buttons or connectors), there are EMC standards that specify limits on this type of ESD through leakage.
thanks, it is unclear for me tge last example, i couldn't notice the part where the onchip gnd is connected to PGND.. could you please clear it a bit, thanks
for that ADC example, even with a GHz Sample rate ADC, it would still be able to capture low frequency products. So anyway we need to split AGND and DGND right?
Is your SNR value near 1? Then maybe... If you are trying to measure a high frequency signal and you are worried about low frequency noise there are much better things you can do to measure the signal above noise without creating an EMI problem by splitting AGND and DGND. Splitting the GND net like that is a poor excuse for controlling noise when someone refuses to learn correct layout and routing practices. In addition, the GND pins on the ADC are connected internally! AGND and DGND splitting just makes the routing in the rest of the board more difficult.
@@Zachariah-Peterson thanks for your comment. I was not thinking straight. Actually for High speed ADC usually it can easily remove those low frequency by digital filter .
I think this video is VERY helpful to me as I am suffering some very serious ground noise inside my ADC board. I'm using FPGA to drive my AD9826 to receive voltage data and I use one single ground as the datasheet told me. But then I found the noise on the ground very high which interrupt the analog signal (in my case, the frequency of the analog signal is very low), do I need to seperate the ground and USE a piece of Ferrite bead to block the clock noise? And if the frequency of the input signal becomes higher (about serval MHz), what should I do to reduce the noise?
Also, if I have several device like this, is making more than one ground connection a good choice?
Maybe I can help you by doing a video demonstrating how to route it correctly....
In the buck converter example, could we have one ground net for these two separate grounds (pins) but carefully layout the pulsed current part (SW node) away from the rest of the circuitry?
Sure you could, but the best strategy for SW node layout is with short connections. The reason is that the connections have their own loop inductance that can generate or receive EMI. That loop inductance is usually something like 5 nH/inch.
I also like one single Gnd for all. Came to that with 3 ADCs on one board, so where to place the NetTie (close to ADC, yes, but wihich? ;) )
Exactly... And some ADCs don't even have separate AGND and DGND pins, it's just a single GND pin. What do you do in that case? Hint: just use a plane!
Make the whole ground plane the net-tie 😉
Thanks Zach, love your content!
Glad you enjoy it!
Different types of isolated pattern layout in pcb design and how to control during pattern plating was not excced pleass explain.
Hi, I don't understand why we need a net tie in the buck converter with the via. I think via connection is a single point anyway, right ? 16:29
It's not a strict requirement. Technically because the PGND and GND pins are being connected with a piece of copper, they will have the same ground potential. The reason this is sometimes done is to control return currents in the plane layer; it enforces some isolation from nearby currents so that they do not interfere with the voltage measurement in the feedback line, and we would like for the feedback line to be either noise free or to only reflect the noise on the power bus in order to provide compensation through the converter's feedback loop. If the insulator layer is much thinner, then you can get away with using a complete piece of ground for your buck converter because any signals that might induce noise on that feedback line will have a more strongly confined distribution of their return current below the trace. It's equivalent to reducing crosstalk between the FB line and some other line.
@@Zachariah-Peterson seems to make sense now. thanks for your reply
In some ADC applications I’ve seen the recommendation to connect analog ground to digital ground through a pi filter. Pros / cons?
I would say definitely not! The aim should be to keep grounds together in terms of voltage, and increasing the impedance between ground nets only encourages ground bounce between the nets. The best place for a pi-filter is connecting the supplies, between DGnd and AGnd, with the capacitor each side connected as close to the respective Gnd pin of the interfacing chip as possible.
No don't do this, it really is better all around to just use continuous ground unless you have a reason not to. @blue5375 mentions ground bounce between the planes, I think he is referring to the fact that the disconnected ground regions can have a potential difference (voltage) between them. The result is that if the potential between those regions starts oscillating, then you have a changing electric field between them that starts radiating, and you have basically created two big edge-coupled patch antennas.
One reason to use different grouns is, for example, with use of an isolated ADC, which requires split grounds but the purpose is for galvanic isolation. I just finished a tutorial with this type of design, you can find the source files on my company website (search for Northwest Engineering Solutions and go to the Design Examples page under the Resources tab).
ugg, GND islands are such a disagreeable topic. As much as I know that return currents can be controlled in placement, I still prefer to carve out AGND separately then use a large Net tie. Once a signal from a sensor, that was on the regular GND, comes into a high impedance input of an op-amp, that's when I consider the signal now on and around AGND. I usually will place my net tie between DGND and AGND right under or around the ADC/DAC or Micro Controller and I'll route the analog signals around the AGND.
Will you explain any holes in this logic?
Not using this old school tried and true way is really hard to break, even when I know it can be done with proper placement and routing.
If you're only keeping the digital stuff in the digital area and the analog stuff in the analog area, and if you can guarantee the digital circuits are completed in the digital section and analog circuits complete in the analog section, then you've basically created an isolated system and the net tie becomes kind of meaningless. In some ways, the net tie is already meaningless because in a non-isolated ADCs the component links the GNDs on the die anyways, the exception is when the ADC is a galvanically isolated component. But with modern ADC packages or an MCU, you might have signals that must route over ground but they can't because of the split. I'm sure you could find some components where the interfaces are separated like you suggest but it is not always like that, just look at mixed signal ASICs or MCUs in quad packages.
I think the biggest problem with the split AGND/DGND guideline is that newbies see it and they don't understand that they shouldn't route across the breaks in ground, but then they do it anyways. Then they wonder why they have excess radiation or fail susceptibility testing.
Thank you
Very helpful
Glad to hear that
When talking about *where* to put the net tie around th-cam.com/video/19WnYPhNOH0/w-d-xo.html ... I missed the answer. As best I could tell, anywhere along the boundary should meet the 0V requirement in theory, and in practice, it seems you would want to be farther away from the chip, since that is something which could temporarily change that. A minute later, when talking about low-frequency analog signals that spread out, I would expect that you want the net tie to be as far as possible from those signals. But you suggested being near the chip, and relatively (given the boundaries) near the analog signal line ... what did I miss?
Actually I'm arguing that if you lay out the board properly then you don't need the net tie at all. If you look at these kinds of recommendations they will put it near the chip or directly under the chip. In the case where you can't control return paths or noise coupling, and then you start splitting GNDs, I think it's much better from a noise perspective to take an isolated design approach but that is much harder, now you have to worry about inductive or optical coulping across ground regions. If you do it wrong you'll have floating grounds that then radiate, it's a pain to do it correctly and it can make the rest of the layout harder.
@@Zachariah-Peterson So the real answer is that you should separate things by enough that you can do it as a single plane, and if you can't do that, try to isolate them completely, and if you can't do that, try to use a single net-tie, but you're already at 3rd-best, so worrying about *where* to put the net-tie is spending your optimization time on the wrong thing? And if you need a rule of thumb even for that, do whatever is conventional and won't make people curious, which often means "near the chip"?
@@jimjjewett If you're at the 3rd best solution then you've probably optimized the wrong stuff and put yourself in a corner where you're now forced to use a net tie instead of a single plane. At that point, might as well near do it the chip I and throw a wonky looking gap between your digital stuff and your analog stuff, but prepare yourself for excess noise!
music is not necessary
But it Sounds welcoming and is done nice in this Video.