The fact that all this knowledge is available for free here is amazing, thanks to Altium for making these videos and thank you Zach for explaining so well!
Great video as always with Zachariah! Years of using I2C and SPI Buses just following the guidelines (and it always worked) but I had never stopped to think that the limitations were related to the OpenDrain and pushpull topollogies of each one. I love these videos because they make you actually think and understand what you are doing.
I have seen such resistors with an SPI memory design, and that stayed looping in my mind looking to what the use of such small resistors and why not something high like driving a diode (At level of 100's or K's). Thank you very much for educative video is comes on time for me. BTW, I like your PCB series, it is hard to find such resources and learn about hidden tricks.
I appreciate SO much that you say what abbreviations are! If anyone disagrees, find an abbreviated diagram of the coagulation cascade, Kreb Cycle, or any other biological diagram. If you understood those without prior knowledge of what those abbreviations stood for, I'll tone down my excitement. 😄
Thank you, layer stackups for these interfaces are quite simple. I2C is basically a slower interface when run in standard mode, its rise time can be on the order of microseconds. With the rise time being that slow a 2-layer board with ground fill on the back layer, or with a ground wire running along the traces, should be enough to suppress radiation. In fast mode and on some modern processors/advanced FPGAs it can have faster rise time and it can get below 100 ns in the fastest cases, for that it is best to use ground fill to help suppress noise if you use 2 layer board. For SPI, the rise time can be very fast, when slower a 2-layer board with ground fill around traces and ground fill on back layer should be okay. In the fastest components with SPI, a 4 layer board might be needed, but those components with
Fantastic, thank you for clearing up the misconceptions regarding Impedance matching, until now I wasn't sure if I should implement controlled impedance for I2C & SPI.
Old electronics servicing peoples like me 40 years before studied person will not not these communication but we are trying to work in this your videos is very useful 👍
Thanks for giving free valuable knowledge. but in our SPI application use pull up resistor 3.3 k ohms SI SO and SCK pin. Is it required or not Please suggest
SPI is a push-pull bus so pull-up resistors are not required. I have seen many different statements about the use of pull-up resistors and they all list different reasons and different pins. The most common suggestion is to use a resistor on the SS/CS pin in order to prevent accidental toggle of the peripheral's state during system startup. The bus will not work without CS and SCK/SCLK signals being present, otherwise it will not respond to SDI/SDO. What is your reasoning for using pullups?
Thank you very much for this awesome educative video. I have one more question, I've seen in some SPI designs that engineers use pull-down resistors(about 1k) between SCK and GND, is this impedance really necessary?
For connecting 5V, 3.3V and 1.8V I2C devices to 5V MCU, via I2C voltage level translators, is it better to use these translators between 5V 3.3V and 5V 1.8V, or 5V 3.3V and 3.3V 1.8V ?
12:45 So if USB requires matched impedance it means they have already build in resistors in transmitters therefore they are already "slowed down". How do you achieve high speed when you have to slow down transmitter for impedance matching?
I would not say that they have "slowed down" anything, they have designed the transmitter such that it has a specific rise time measured at the output pin when the signal encounters a 50 Ohm single-ended impedance. They didn't design it to one rise time and then add stuff to slow it down. When you see a rise time spec in a datasheet, that number they quote is the number you can expect to measure on that trace, it doesn't really matter what happens inside the transmitter because they have already designed it to operate with a 50 Ohm trace. This is why you would not intentionally place series resistors on the USB outputs when they are already rated for 50 Ohms single-ended impedance.
Wait, so how does the series termination resistor limit rise times? I thought it was more to limit signal reflections. To my knowledge using a series resistor would certainly limit the current, but I don't see how it could have a capacitive effect with respect to the rise time. Is there anything I'm missing or over-simplifying here?
Imagine the resistor and load+bus capacitance as an RC circuit, increasing the resistor value would increase the charge time of the capacitor - equivalent to slowing the rise time
Yes the series resistor does limit the rise times. It slows down the edge rate because it is equivalent to adding some DC resistance into a circuit with capacitance (in the lumped element view); this basically adds damping to the transient response. If you had a short connection between the driver and the receiver component, you would get the same effect, you basically have an RC circuit that is charging or discharging, so adding some resistance increases the time constant.
Thank you for the video! I am actually designing a project which interconnects two PCBs and a use a flat cable between the 2 for I2C. Furthermore, the 2nd pcb is quite long (about 30cm). Are there any further considerations I should take into account for this PCB routing? Thank you in advance! 😄 keep it up I am learning tons!
Make sure that the GND is always carried solidly. Keep the data lines roughly the same length. Pullups on both sides can help. 30cm is short for I2C, but it depends on how fast you run the I2C. Faster means shorter. Philips invented the I2C bus to make it easier to control the many ICs in radio and tube TV sets. The goal was always to implement many tasks flexibly using a bus with few pins. Every PC today uses I2C for secondary tasks such as fan control, temperature measurement or LEDs blinking.
Yes 1) add 15pF caps on SCL and SDA - it helps to filter out noise, which is particularly relevant for long traces/cables 2) follow 60-40 rule for the 0V pins ratio on FCC cable, i.e. for a 10-pin FCC, 6 pins should be signal, 4 pins should be 0V 3) I typically add series resistors on SCL and SDA as well on driver side, like Zach said in the video. The frequency of SCL can actually be up to 3.4MHz, depending on the design. There're also practical benefits - they limit current in case of a fault or ESD; it's easier to attach logic analyser to a resistor than to a trace; etc.
@DrEMC-sf8rx 1) by adding capacitance you make the rise times even slower, in anlong cable/pcb situation shouldn' it be avoided? since long trace means more capacitance to charge up and slower max speed achievable 3) same for series resistor
Very useful info. please make more videos on series and parallel termination resistor reasons and how to route them. for example, using series termination on EXT SDRAM CLK or Parallel Termination ON Diff Pair CLKs Cases. In my case, we have a graphical Circuit with EXT SDRAM as FrameBuffer and MIPI-DSI as LCD Interface but the Data gets Corrupted. using termination can help? How Much Length match will be fine for EXT SDRAM Signals? It's On Two Layer Board With STM32F7 On Top and EXT SDRAM On the Bottom side beneath the Microcontroller and MIPI DSI Lanes as close as possible to the Micro Pins (Around 23 mm Away). All SDRAM Signals Are Between 18 to 37 mm Long Traces, and Delays On ACC, BL0, and BL1 Groups are less than 100ps. What Will be the reasons for Corrupted Data, Data Gets to the LCD But It Gets Corruption in Nearby pixels. Using 4 Layer PCB Can Solve the Problem?
If you are not doing MIPI DSI and SDRAM routing on a 4 layer board, then I am not surprised that you are having a problem. I do not know if it is specifically crosstalk or you did not design to the correct impedance, but if you have an interface like DSI or SDRAM then you must design to the correct impedance. Don't use these things like critical length rule because everyone uses them incorrectly (I explained why in another video). And don't apply termination to a component that has an interface with an impedance requirement; that impedance requirement means that the traces just need to be designed to that impedance; the termination circuit will already exist on the semiconductor die. The only cases where you should be applying any kind of termination circuit with discrete components is when 1) the component datasheet tells you to apply it externally; and 2) you are working with RF components below 5 GHz where the output impedance from your RF source will have some reactance.
Very good video except for the signal rise time increase from 1ns to 10ns from a 22R termination resistor. I am running 2.5ns rise times with 22R terminators just fine.
Well I just stated those numbers as a conceptual example, it is not a hard rule that it goes from 1ns to 10ns. I have also used some ASICs that also maintain very fast rise time with long traces and with the series resistors.
Hi Zach, i'm studying on I2C electrical specification recently. and i have a question on the validation item--> setup time for re-start condition. i'm wondering why it's more important to define setup time for re-start condition than setup time for START condition? i think it's neccessary to define setup time for start condition since there's always a START on every transmitting procedure. but the re-start condition isn't that frequently appeared. do you have any idea on this? appreciate if you reply, thanks
Yes the term "rise time" refers to the low-to-high signal transition, but sometimes it is used interchangeably for the high-to-low transition time. Sometimes you will see "rise/fall time" if the two values are similar.
What about I2S? I'm a hobbyist who wants to experiment with STM32 and some audio codecs but I tried an AD1937 and can't get it to work. I can get the I2C communication working with it, but I suspect the I2S is suffering from ringing. I think I can actually see some ringing on my scope. But then in some I2S videos on TH-cam I see people soldering loose wires without any concern for impedance at all. So I'm kind of lost. In a design for a Dev kit with this chip, I saw some impedance matching on the I2S lines, just a couple pF and a few ohms. But it's hard to figure out whether I'm dealing with a software issue or whether I did something wrong in my hardware design. Maybe I'm not configuring the codec correctly.. Should I definitely have the codec and STM32 on the same pcb? If so then why does it seem some people can get I2S working over some loose wires? Would you recommend I start with a more simple codec first?
Hi Zack, I watched this video again today and I had one question. When should we terminate a load like 50 ohm near receiver side if the datasheet doesn't point out input impedance inside receiver? From the video, it looks like there's only one termination used for driver side.
The loads you would place on an SPI/I2C link do not have an impedance specification, they are integrated circuits and they do not have a specific impedance. They are purely voltage controlled so they only have a high input impedance because SPI receiver circuits are essentially FET inputs. Part of the reason for a series terminator on the driver is to slow down the bus a little bit to make up for a low bus/load capacitance, this can help pass EMC but it also matches the impedance when the line is very long. That impedance matching plays a dual role of preventing reflections, but it does this by slowing down the bus so that the bus is always electrically short enough to work properly.
Impedance is a fundamental property of structures that guide electromagnetic waves. All the copper lines on a PCB are guiding an electromagnetic wave between two components, and these copper lines are called traces. The term "trace impedance" refers to the impedance of these copper lines.
It surprised me a non-asian person pronounce I-two-C. I thought it was a mistake asian people made. Here we call it I-two-C or I-tsuu-C and some people in Taiwan call it I-su-kwe-C.
Not in the same sense that we think about length matching or timing in a parallel bus like DDR4. There is a timing requirement between the clock and signal, but that is a pretty generous limit. IF you want to try and apply length matching rules from a high-speed design to SPI, just stop and think about the rise times I've listed here... You're generally going to be in the nanosecond range and there will be some timing spec to be met at the receiver. Just as an example, let's say we have a 1 ns signal on a Dk = 4 laminate (internal layer for convenience), the length traveled by the signal during its rise time is 15 cm. If, for length matching on a parallel bus, you take a 25% UI value for the allowed skew between sigansl then you get a 3.75 cm allowed mismatch between two signals. The timing spec for that pair of signals might produce a distance mismatch of a similar value. Just make sure you look at the datasheet for the receiver to get the required timing spec and use that to determine an allowed length mismatch.
VERY Bad idea to put a source termination on the SCK line with multiple loads. This will not ensure that the rise/falls are monatonic. They will tend to flatten right at the 1/2 way point until the end reflection brings them back.
There is a timing margin specification, but this depends on the clock frequency and the rise time of the signals. It is not the same type of length matching we do with differential pairs, where the clock can be embedded in the serial bitstream and the two opposite polarity signals need to be aligned along their edge rate. The logic transition relative to clock and CS setup and hold times needs to happen within some timing margin that depends on the time between clock transitions. If the clock rate is slow and the interface is fast (this is pretty typical on advanced ASICs with low load capacitance), then the timing margin between two signals can be somewhat large, and this can allow pretty large length mismatch allowance between the signals on the bus.
It's a good video. Exactly get how to determine an expected rise time and fall time. But just a little be confused with the Topic, protocol explained. The protocol probably will refer to the rule for transmitter and receiver both when they exchange data. Like how to tell and define start bit, data frame, stop bit, and ack bit.
There are multiple videos where I've shown it on a PCB. I was talking about some of the routing rules on a PCB and what the topology looks like so that users know how to route it. Do you want to see some examples with explanations?
The fact that all this knowledge is available for free here is amazing, thanks to Altium for making these videos and thank you Zach for explaining so well!
You're very welcome!
This is physics, it is common knowledge. Not a secret
I love this channel because it teaches how to fish instead of giving fish. Thanks my best HW teacher Zach Peterson :)
Glad you enjoy it!
Excellent explanation of the SPI "impedance matching".
Glad it was helpful!
Great video as always with Zachariah! Years of using I2C and SPI Buses just following the guidelines (and it always worked) but I had never stopped to think that the limitations were related to the OpenDrain and pushpull topollogies of each one.
I love these videos because they make you actually think and understand what you are doing.
That is awesome!
Where can I get those guidelines for such PCB designs like I2C ,SPI .... Could you please share the links??
I have seen such resistors with an SPI memory design, and that stayed looping in my mind looking to what the use of such small resistors and why not something high like driving a diode (At level of 100's or K's).
Thank you very much for educative video is comes on time for me. BTW, I like your PCB series, it is hard to find such resources and learn about hidden tricks.
I appreciate SO much that you say what abbreviations are! If anyone disagrees, find an abbreviated diagram of the coagulation cascade, Kreb Cycle, or any other biological diagram. If you understood those without prior knowledge of what those abbreviations stood for, I'll tone down my excitement. 😄
Clear, informative, and exactly my speed. Thank you!
Great to hear!
Very informational video that clearly describes how I2C and SPI work on a PCB. My question is how would a layer stack up look like for those examples?
Thank you, layer stackups for these interfaces are quite simple. I2C is basically a slower interface when run in standard mode, its rise time can be on the order of microseconds. With the rise time being that slow a 2-layer board with ground fill on the back layer, or with a ground wire running along the traces, should be enough to suppress radiation. In fast mode and on some modern processors/advanced FPGAs it can have faster rise time and it can get below 100 ns in the fastest cases, for that it is best to use ground fill to help suppress noise if you use 2 layer board. For SPI, the rise time can be very fast, when slower a 2-layer board with ground fill around traces and ground fill on back layer should be okay. In the fastest components with SPI, a 4 layer board might be needed, but those components with
Fantastic, thank you for clearing up the misconceptions regarding Impedance matching, until now I wasn't sure if I should implement controlled impedance for I2C & SPI.
Old electronics servicing peoples like me 40 years before studied person will not not these communication but we are trying to work in this your videos is very useful 👍
Very useful info for my undergrad senior project! Thanks, Zack!
Glad it was helpful!
Thank you! Please tell us more themes about developing PCBs.
We’ve got a ton on the channel! What kind of thing are you looking for?
Thanks for the video) Can you talk more about SPI bus tips and tricks like optimal level shifting technics or pull-up/down resistors.
Great suggestion!
Merci beaucoup, ça me démystifie ces 2 protocoles dont l'I2C que je prévois de faire un PCB
It can't get anymore simple than this. Thank you soo much howtobasic!
Thank you for this. Confirmed a few things I had already thought. Awesome.
Wonderful!
Awesome
Video!
Wanted to know how to test these peripherals In a software testing role
Thanks for giving free valuable knowledge. but in our SPI application use pull up resistor 3.3 k ohms SI SO and SCK pin. Is it required or not Please suggest
SPI is a push-pull bus so pull-up resistors are not required. I have seen many different statements about the use of pull-up resistors and they all list different reasons and different pins. The most common suggestion is to use a resistor on the SS/CS pin in order to prevent accidental toggle of the peripheral's state during system startup. The bus will not work without CS and SCK/SCLK signals being present, otherwise it will not respond to SDI/SDO. What is your reasoning for using pullups?
How to validate the spi flash memories.
What are the things we have to consider.
Thank you very much for this awesome educative video. I have one more question, I've seen in some SPI designs that engineers use pull-down resistors(about 1k) between SCK and GND, is this impedance really necessary?
Necessary? Technically no, but its one of those things that if you want to maybe build in a spot to test the line, it is a useful thing to have.
Excellent video, please do SDIO/MMC and DDR next.
Great suggestion!
That is actually a better definition using chip select instead of slave select, just from a memory point of view.
For connecting 5V, 3.3V and 1.8V I2C devices to 5V MCU, via I2C voltage level translators, is it better to use these translators between 5V 3.3V and 5V 1.8V, or 5V 3.3V and 3.3V 1.8V ?
So thankful for this
12:45 So if USB requires matched impedance it means they have already build in resistors in transmitters therefore they are already "slowed down". How do you achieve high speed when you have to slow down transmitter for impedance matching?
I would not say that they have "slowed down" anything, they have designed the transmitter such that it has a specific rise time measured at the output pin when the signal encounters a 50 Ohm single-ended impedance. They didn't design it to one rise time and then add stuff to slow it down. When you see a rise time spec in a datasheet, that number they quote is the number you can expect to measure on that trace, it doesn't really matter what happens inside the transmitter because they have already designed it to operate with a 50 Ohm trace. This is why you would not intentionally place series resistors on the USB outputs when they are already rated for 50 Ohms single-ended impedance.
Nice info, well done, thanks for sharing it with us :)
Wait, so how does the series termination resistor limit rise times? I thought it was more to limit signal reflections. To my knowledge using a series resistor would certainly limit the current, but I don't see how it could have a capacitive effect with respect to the rise time. Is there anything I'm missing or over-simplifying here?
Imagine the resistor and load+bus capacitance as an RC circuit, increasing the resistor value would increase the charge time of the capacitor - equivalent to slowing the rise time
Yes the series resistor does limit the rise times. It slows down the edge rate because it is equivalent to adding some DC resistance into a circuit with capacitance (in the lumped element view); this basically adds damping to the transient response. If you had a short connection between the driver and the receiver component, you would get the same effect, you basically have an RC circuit that is charging or discharging, so adding some resistance increases the time constant.
@@Zachariah-Peterson @Philip Canete, Thanks guys. I guess I forgot about the R part in RC time constants.
Thank you for the video!
I am actually designing a project which interconnects two PCBs and a use a flat cable between the 2 for I2C. Furthermore, the 2nd pcb is quite long (about 30cm). Are there any further considerations I should take into account for this PCB routing?
Thank you in advance! 😄 keep it up I am learning tons!
Make sure that the GND is always carried solidly.
Keep the data lines roughly the same length.
Pullups on both sides can help.
30cm is short for I2C, but it depends on how fast you run the I2C.
Faster means shorter.
Philips invented the I2C bus to make it easier to control the many ICs in radio and tube TV sets.
The goal was always to implement many tasks flexibly using a bus with few pins.
Every PC today uses I2C for secondary tasks such as fan control, temperature measurement or LEDs blinking.
Yes
1) add 15pF caps on SCL and SDA - it helps to filter out noise, which is particularly relevant for long traces/cables
2) follow 60-40 rule for the 0V pins ratio on FCC cable, i.e. for a 10-pin FCC, 6 pins should be signal, 4 pins should be 0V
3) I typically add series resistors on SCL and SDA as well on driver side, like Zach said in the video. The frequency of SCL can actually be up to 3.4MHz, depending on the design. There're also practical benefits - they limit current in case of a fault or ESD; it's easier to attach logic analyser to a resistor than to a trace; etc.
@DrEMC-sf8rx
1) by adding capacitance you make the rise times even slower, in anlong cable/pcb situation shouldn' it be avoided? since long trace means more capacitance to charge up and slower max speed achievable
3) same for series resistor
Very useful info. please make more videos on series and parallel termination resistor reasons and how to route them. for example, using series termination on EXT SDRAM CLK or Parallel Termination ON Diff Pair CLKs Cases. In my case, we have a graphical Circuit with EXT SDRAM as FrameBuffer and MIPI-DSI as LCD Interface but the Data gets Corrupted. using termination can help? How Much Length match will be fine for EXT SDRAM Signals? It's On Two Layer Board With STM32F7 On Top and EXT SDRAM On the Bottom side beneath the Microcontroller and MIPI DSI Lanes as close as possible to the Micro Pins (Around 23 mm Away). All SDRAM Signals Are Between 18 to 37 mm Long Traces, and Delays On ACC, BL0, and BL1 Groups are less than 100ps. What Will be the reasons for Corrupted Data, Data Gets to the LCD But It Gets Corruption in Nearby pixels. Using 4 Layer PCB Can Solve the Problem?
If you are not doing MIPI DSI and SDRAM routing on a 4 layer board, then I am not surprised that you are having a problem. I do not know if it is specifically crosstalk or you did not design to the correct impedance, but if you have an interface like DSI or SDRAM then you must design to the correct impedance. Don't use these things like critical length rule because everyone uses them incorrectly (I explained why in another video). And don't apply termination to a component that has an interface with an impedance requirement; that impedance requirement means that the traces just need to be designed to that impedance; the termination circuit will already exist on the semiconductor die. The only cases where you should be applying any kind of termination circuit with discrete components is when 1) the component datasheet tells you to apply it externally; and 2) you are working with RF components below 5 GHz where the output impedance from your RF source will have some reactance.
Very good video except for the signal rise time increase from 1ns to 10ns from a 22R termination resistor. I am running 2.5ns rise times with 22R terminators just fine.
Well I just stated those numbers as a conceptual example, it is not a hard rule that it goes from 1ns to 10ns. I have also used some ASICs that also maintain very fast rise time with long traces and with the series resistors.
thanks bud, dunno what this is but just stoned letting it absorb into my subconscious at its free will
Hi Zach, i'm studying on I2C electrical specification recently.
and i have a question on the validation item--> setup time for re-start condition.
i'm wondering why it's more important to define setup time for re-start condition than setup time for START condition?
i think it's neccessary to define setup time for start condition since there's always a START on every transmitting procedure.
but the re-start condition isn't that frequently appeared.
do you have any idea on this?
appreciate if you reply, thanks
Great, Thank you :)
Very interesting. Thank you.
Glad you enjoyed it
Amazing
Thanks
Execuse me sir, here by rise time do you mean the time required for the signal to go high from low?
Yes the term "rise time" refers to the low-to-high signal transition, but sometimes it is used interchangeably for the high-to-low transition time. Sometimes you will see "rise/fall time" if the two values are similar.
What about I2S? I'm a hobbyist who wants to experiment with STM32 and some audio codecs but I tried an AD1937 and can't get it to work. I can get the I2C communication working with it, but I suspect the I2S is suffering from ringing. I think I can actually see some ringing on my scope. But then in some I2S videos on TH-cam I see people soldering loose wires without any concern for impedance at all. So I'm kind of lost. In a design for a Dev kit with this chip, I saw some impedance matching on the I2S lines, just a couple pF and a few ohms. But it's hard to figure out whether I'm dealing with a software issue or whether I did something wrong in my hardware design. Maybe I'm not configuring the codec correctly.. Should I definitely have the codec and STM32 on the same pcb? If so then why does it seem some people can get I2S working over some loose wires? Would you recommend I start with a more simple codec first?
Hi Zack, I watched this video again today and I had one question. When should we terminate a load like 50 ohm near receiver side if the datasheet doesn't point out input impedance inside receiver? From the video, it looks like there's only one termination used for driver side.
The loads you would place on an SPI/I2C link do not have an impedance specification, they are integrated circuits and they do not have a specific impedance. They are purely voltage controlled so they only have a high input impedance because SPI receiver circuits are essentially FET inputs. Part of the reason for a series terminator on the driver is to slow down the bus a little bit to make up for a low bus/load capacitance, this can help pass EMC but it also matches the impedance when the line is very long. That impedance matching plays a dual role of preventing reflections, but it does this by slowing down the bus so that the bus is always electrically short enough to work properly.
@@Zachariah-Peterson Thank you, Noted!
Красавчик, классно объясняешь.
looks like ryan from the office :p
good, thanks
Nice video!
Great video!!!
Glad you liked it!
Excellent 😁
Thanks 😁
How working the signal I3S and Slimbus?
That would be a really great topic, I do not use I3C often but I should do a video on it!
I have always wondered why there were 33ohm resistors in series on CS pins ... some datasheets are poorly written
Sometimes it's not even mentioned in datasheets, and there is not a specific method to calculate.
Trace impedance, are they the same as those squiggly lines you see on the pcb?
Impedance is a fundamental property of structures that guide electromagnetic waves. All the copper lines on a PCB are guiding an electromagnetic wave between two components, and these copper lines are called traces. The term "trace impedance" refers to the impedance of these copper lines.
Hello! I send a data packet "slave func data srs16", but the result is this signal "00 slave func data srs16". Why do two zeros appear? ModbusRTU
I can't answer that I would need to know what component you are referring to.
You are awesome! 👏
You too!!
really good video cool stuff, very helpful :)
Glad you think so!
thanks
thanks 😍🙏🏻
It surprised me a non-asian person pronounce I-two-C. I thought it was a mistake asian people made. Here we call it I-two-C or I-tsuu-C and some people in Taiwan call it I-su-kwe-C.
The protocol is called "I squared C", but I always got in the habit of saying "I-2-C" after hearing other people say this
Thank you so much Sir. It cleared my doubts. Is there any requirement of signal's length matching in between MISO, MOSI & SCK ?
Master In Slave Out
Master Out Slave IN
SCK Clock
Chip Select, Low = selected
The data sheet of the IC gives you the necessary timing specifications.
Not in the same sense that we think about length matching or timing in a parallel bus like DDR4. There is a timing requirement between the clock and signal, but that is a pretty generous limit. IF you want to try and apply length matching rules from a high-speed design to SPI, just stop and think about the rise times I've listed here... You're generally going to be in the nanosecond range and there will be some timing spec to be met at the receiver. Just as an example, let's say we have a 1 ns signal on a Dk = 4 laminate (internal layer for convenience), the length traveled by the signal during its rise time is 15 cm. If, for length matching on a parallel bus, you take a 25% UI value for the allowed skew between sigansl then you get a 3.75 cm allowed mismatch between two signals. The timing spec for that pair of signals might produce a distance mismatch of a similar value. Just make sure you look at the datasheet for the receiver to get the required timing spec and use that to determine an allowed length mismatch.
@@Zachariah-Peterson thank you so much sir. 👍
First time I heard i²c called i2c.
Well everyone writes it i2c instead of i²c, so....
VERY Bad idea to put a source termination on the SCK line with multiple loads. This will not ensure that the rise/falls are monatonic. They will tend to flatten right at the 1/2 way point until the end reflection brings them back.
In SPI need to do a length matching .If we are usung multiple slaves .
There is a timing margin specification, but this depends on the clock frequency and the rise time of the signals. It is not the same type of length matching we do with differential pairs, where the clock can be embedded in the serial bitstream and the two opposite polarity signals need to be aligned along their edge rate. The logic transition relative to clock and CS setup and hold times needs to happen within some timing margin that depends on the time between clock transitions. If the clock rate is slow and the interface is fast (this is pretty typical on advanced ASICs with low load capacitance), then the timing margin between two signals can be somewhat large, and this can allow pretty large length mismatch allowance between the signals on the bus.
seen
It's a good video. Exactly get how to determine an expected rise time and fall time. But just a little be confused with the Topic, protocol explained. The protocol probably will refer to the rule for transmitter and receiver both when they exchange data. Like how to tell and define start bit, data frame, stop bit, and ack bit.
Thanks, since this is a PCB channel I wanted to focus on the PCB aspects but we'll put together something on the data formats
I agree. "Protocol" is the not the best way to describe what this video is about.
@@BTLag Well then we change it
Why didn't you show it on an PCB??
There are multiple videos where I've shown it on a PCB. I was talking about some of the routing rules on a PCB and what the topology looks like so that users know how to route it. Do you want to see some examples with explanations?
ay quá chừng luôn
Should also mention that MISO may need a pull-up or pull down.
Good point
like+sub, gj
✌
you even know I2C.😂 you know everything🙃
why is it outstanding?
Everybody should know a little I2C
@@enginstud8852 coz it's kooool~~
How old are you? Four?
@@MichaelKingsfordGray 3😔