Having spent many years in EMI labs looking at radiated emissions, I can verify that the more continuous the ground plane, the better it is. Thank You.
Thanks Zach, super helpful video even for a professional. You get all this talk of "star grounding" and "single point ground" but it turns out that the lazy way of just one big copper pour is all you need.
Thank you Zach. I have remembered that, my teacher told me to separate ground plane for mixed signal boards. Now I understood, it's necessary to have continuous return path.
Hi Rukshan, glad you found the advice helpful. There are some instances where we need to separate grounds, but in most cases it makes layout more difficult and encourages bad routing practices. There is a new video coming up that will outline some cases where separate ground are necessary.
4:04 Return path is probably in the power supply lines. In many cases, a signal will "see" any DC rail as ground. We actually exploit HT as a ground in many valve guitar amps by placing bypass capacitors across anode resistors to keep the higher-gain stages from oscillating.
I remember cutting up gnd plane via ferrite; it created a serious problem of RF Transmission not getting enough power due to ground bounce. Later shorted the GND and the board worked fine
Zach, in the next videos you can indicate design considerations with the FR4 PCB material for 2 and 4 layers, ground routing and Vcc. Also, advice on the ground and Vcc planes when isolating with an optocoupler or transformer (Pulse) to control a power semiconductor. This last point is of great interest. Thanks.
Hi Victor, great idea! I've gotten a lot of questions about using 4-layer boards with or without isolation, including in power systems. I've got this one cued up for filming this week. Stay tuned for more videos!
Hi Zach, thanks for sharing this topic. Here is my question, I’ve seen some mix signals boards in my company that use a ferrite bead to separate analog GND and digital GND. Even power GND and so on. I don’t totally agree with this grounding method. How is your opinion about using FBs cutting the grounds?
Terrible design choice. It only eliminates the DC offset by setting the two grounds together so they only do not radiate very close to DC. However, that's not really the noise we tend to care about unless we are using an isolated supply with 60 Hz and a chassis, in which case you can get a current loop through the chassis that appears on your output. The ferrite bead still leaves high impedance between the two regions somewhere from 100 MHz to 1 GHz. If there is any current oscillating in those frequencies, it will induce an image current in the other plane, and the two planes together act like a pair of coupled patch antennas. These can radiate and the result is the device might fail EMC. This is one reason that, even when cutting a design into two regions, fast digital signals on the digital region in the DGND region could still produce some excess radiated emissions.
@@Zachariah-Peterson Let me self-questioning my question. After watching the new episode of "Bridging Grounds with Ferrites? TERRIBLE IDEA!!!". It really solved my question.
Hi Zach! Thanks so much for this very valuable content. Great format, clean and concise explanations 👍🏻 I was wondering if you could cover analog and mixed-signal audio design/layout strategies in the future? I have noticed a lot of contradiction regarding guidelines online. Thanks !
I can't convince the company I'm at now to accept a one ground approach. The engineers insist on splitting planes and tying them together at an SPG point. Any suggestions for resources I can use to prove that the one ground approach is better?
Are they trying to route stuff over the gap between those plane regions, or do the components in each region stay in one area and do not require routing signals between them? If they are not routing any signals between the two regions or they are routing only across the region near the SPG then the board could technically work fine but it's more difficult to design. Maybe take a board that was built their way, place and route the same board without an SPG, and see if you can do it better and with less noise?
Hello Zach, I am designing an amplifier consisting of 3 or 4 high-speed Op-amps and in all of the datasheets it says that a window should be opened in the ground plane under the input and output pins, to minimize the capacitance. Does that also create return path and EMI problems? How do I deal with that?
I will just say that it depends, those inputs are high impedance, so the intention is to reduce the capacitive loading at the input pin. You can compare the capacitance on the input pin to the capacitance of the trace. The trace capacitance will be on the order of 3 pF/inch, whereas the op-amp input pin could range anywhere from sub-pF to high pF. If the input capacitance is large then the trace won't matter unless you have other reactive components in the feedback loop. The other thing that can happen with op-amps is that they exhibit an underdamped oscillation on the output when there is excess inductance in the feedback loop and excess capacitance at the summing node, but this is more of a problem when the gain bandwidth products are very high. What is the part number you are using?
Sometimes I feel guilty of not following the datasheet's recommendation of separating ground planes (which in the real world is sometimes impossible to do). Thanks for this, I've been doing it right all along, ha!
So does this mean I shouldn't even worry about distinguishing between AGND and DGND? They should both just immediately connect to the single, main ground plane?
You should not worry about distinguishing between AGND and DGND except in an isolated ADC or some other isolated component. In an ADC or DAC these will be connected together on the component die. As far as routing is concerned to impact return paths, when in the audio range it can help to intentionally route the ground for a signal alognside the trace, or use a differential pair. But this is not the same thing as using separate ground regions.
Route things on opposite surface layers, or put some routing on internal layers. As you get small your layer count tends to go up because, at some point, that is the only way to fit traces into the PCB. Also you can reduce layer thickness while keeping the spacing between nets constant, this will always help reduce crosstalk.
Thank you for these explanations but lots of manufacturers' application notes recommend 2 ground regions for example for signal buffering IC's on the internet. They recommend 2 ground regions : one on the left small signal input section of the IC and another region on the right output side . However they all also show a thin connection to the 2 grounds. So kindly how do you explain that?
Hello IHT sarl, What you just described is a lot like a star ground and it's a typical recommendation you will see for some signal interface ICs. Two examples that come to mind are interface converters (like SPI to I2C, etc.), level converters, and ADCs. In what you described, the grounds are being connected at some point so both regions will have the same potential. This is often recommended for isolation because the IC manufacturer is trying to help you prevent signals on the IOs from interfering. The problem with it is that you can only route other signals over the continuous ground section without creating an EMI source, so it makes correct routing more difficult. In the case of an ADC, the pin naming might convince you to try something similar, but I've seen an Analog Devices note that better explains this and states explicitly the various DGND and AGND pins should be tied together externally.
I think most designers that deal with a lot of EMI problems will agree that application notes should sometimes be viewed with suspicion, or the recommendation should at least be tested first. Just be careful about blindly following application notes and reference designs, because the recommendations might not always be best for your specific system. It's one thing if you are just replicating their test board or evaluation product, it's totally different if you are designing a custom board or adding to an existing board.
amazing video. thank you. I have a question. Recently i was designing a part of Li-ion charging . in that part i used a chip MAX8724 . surprising fact that i have found split ground place for PGND and GND in their Evaluation kit. it was a 6 layer board. could you please explain that why is that split ground was done? Normally i use solid GND place and use different blocks in different regions just as you shown. but after building the circuit in my way it didn't work . what could be the possible reasons for that? again, thank you very much for what you are doing for us.
If you look at the datasheet for the MAX8724, you'll see that they do connect those grounds together. I'll make a video of this showing how to do it. The answer is on page 16 of the datasheet. You'll notice that they connected PGND and GND right by the battery. So they are designed with a single GND net, just not a large plane everywhere. You would want to use a net tie to make that connection right by the battery connector.
Using a full ground plane, do you recommend using the AC (120volts) on 1 layer (Top), gnd layer (middle), and digital layer (bottom). To separate the signals with a ground layer?
@Phạm Chiến Trung I’ve also seen that, my issue is the pcb convert AC to 12v 5V and 3v. With that I use moc3083 to switch ac power going to lamp ballast. So I need all in one board :-$
I'm going to assume this was done in an isolated DC/DC converter, because the standard guidance is to use a Y-type safety capacitor in order to maintain the galvanic isolation at DC. This generally does not create a radiated EMI problem as long as signals originating on the secondary side of your DC/DC converter are not routed over to the primary side. This includes any feedback signal, which needs to come back to the switching driver on the primary side using an optocoupler. The only potential EMI/EMC problem is leakage current through the Y-type capacitor and onto any connectors or terminals, some industry specific EMC standards (e.g., medical) have very low leakage current requirements and it might be difficult to find a capacitor that offers the high voltage rating and low leakage in the right capacitor values.
Can we have a details demonstration video regarding all the possible scenarios of EMI issues in a PCB and current EMC checking process that an industry follows and minimum guidelines have to be met to make a product released in market?
So if I have IIC devices on 2 different board (with different GND plane) . Is it Ok to just connect them by a 2 pin cable ? (SDA/sCLK), is that one of typical scenario you don’t know where the return path is and there would be EMI problem?
Best practice is to use a 3-pin connector that includes a ground trace, especially if there is no reason to keep the grounds fully isolated. Just connect the GNDs with the GND wire.
For a mix signal system with 0-5V power rail, 2.5V reference, would the signal return path be in the 2.5V reference plane? How to hand this "virtual ground"?
Hey Zach, thanks for the really informative video. I was wondering though, if you route the (DC) power supply in a U shape around some Digital or Analogue sections of your PCB to supply some components on the other side of the board, wouldn't it be advisable to route the GND (so the return path) for that DC power supply also in a U shape? Because with the Low frequency of the DC Power supply the return current would not travel underneath the forward path but rather take the shortest way back, and interfere with those of my components placed inside U shaped Trace right? Greetings, David
If you happened to route DC in a U shape and you wanted a return path to follow the same shape, then you would want to also shape the returning conductor into a U shape. I wasn't trying to say that any kind of U shape route is how this will turn out in reality or that you will always do this, it is meant to be a simple example. But you are correct that the DC return won't follow the power conductor, for truly DC power this occurs because the return current is not being induced capacitively into the return conductor.
I'm a ECE student and design hardware. In my recent project, I designed an ESP32 based LoRa Sx1276 where I had to use the SX1276 chip instead of Ready made SoC module. What I did is just separated the LoRa Section and Placed Via Fence around. I created GND plane for rest of the PCB but left the LoRa section. Is this approach legit? Thanks
It sounds like you made the right approach, but I don't like to make promises unless I can see the layout. If you want, you can send me a private message.
Sometimes you have a very small board where you have to pack several analog channels and the corresponding digital section to control and capture these analog signals. In this case you don't have space to really separate analog from digital. When this happens, it is ok to split the planes, even create GND plane "sections" for each analog channel using keepout lines in order to contain the fields The important thing, as you mention, is to make sure you absolutely don't route over the slots and you have a clear an uninterrupted return path for all your signals. You will have this "bridge" of continuous GND plane for the tracks interfacing the digital and analog sections but each analog section will have its own GND plane section created using keepout lines.
Manuel, I totally agree, it's appropriate to make the split in certain situations. In some cases it's even preferable. The point about return path is critical and so many people get in trouble with this, so I find it's best for some designers to do the safe thing and just use a plane layer to provide the return path.
I don't see how it would be preferable in that case to split the ground plane. Wouldn't it be better in that case to keep a continuous ground and use a via wall between analog and digital? I think the only use case of split ground is when you have galvanically isolated sections that only commumicate or exchange power via optocouplers or transformers, capacitors or some other means.
Why don't you just use a Wire to connect to two or more isolated GND planes on the same PCB circuit? I see a lot of companies like TI use this kind of method when they have an isolated GND planes on their boards.
Hi...your videos really helpful That you mentioned in video use same gnd uniformly on both analog and digital..but is it good pratice to give analog gnd(gnd present in analog circuit) under digital gnd plane @Zachariah Peterson
Having spent many years in EMI labs looking at radiated emissions, I can verify that the more continuous the ground plane, the better it is. Thank You.
Man, I'm absolutely loving this series. So helpful
Glad you like them!
Thanks Zach, super helpful video even for a professional. You get all this talk of "star grounding" and "single point ground" but it turns out that the lazy way of just one big copper pour is all you need.
Thank you Zach. I have remembered that, my teacher told me to separate ground plane for mixed signal boards. Now I understood, it's necessary to have continuous return path.
Hi Rukshan, glad you found the advice helpful. There are some instances where we need to separate grounds, but in most cases it makes layout more difficult and encourages bad routing practices. There is a new video coming up that will outline some cases where separate ground are necessary.
wonderful explanation
4:04 Return path is probably in the power supply lines. In many cases, a signal will "see" any DC rail as ground. We actually exploit HT as a ground in many valve guitar amps by placing bypass capacitors across anode resistors to keep the higher-gain stages from oscillating.
Thank you so much ❤. How can i rout ddr3 and ps FPGA ?
I remember cutting up gnd plane via ferrite; it created a serious problem of RF Transmission not getting enough power due to ground bounce. Later shorted the GND and the board worked fine
Zach, in the next videos you can indicate design considerations with the FR4 PCB material for 2 and 4 layers, ground routing and Vcc.
Also, advice on the ground and Vcc planes when isolating with an optocoupler or transformer (Pulse) to control a power semiconductor. This last point is of great interest. Thanks.
Thats a good question
Hi Victor, great idea! I've gotten a lot of questions about using 4-layer boards with or without isolation, including in power systems. I've got this one cued up for filming this week. Stay tuned for more videos!
It was very helpful. Thanks for sharing your information!
So glad!
Hi Zach, thanks for sharing this topic. Here is my question, I’ve seen some mix signals boards in my company that use a ferrite bead to separate analog GND and digital GND. Even power GND and so on. I don’t totally agree with this grounding method. How is your opinion about using FBs cutting the grounds?
Terrible design choice. It only eliminates the DC offset by setting the two grounds together so they only do not radiate very close to DC. However, that's not really the noise we tend to care about unless we are using an isolated supply with 60 Hz and a chassis, in which case you can get a current loop through the chassis that appears on your output.
The ferrite bead still leaves high impedance between the two regions somewhere from 100 MHz to 1 GHz. If there is any current oscillating in those frequencies, it will induce an image current in the other plane, and the two planes together act like a pair of coupled patch antennas. These can radiate and the result is the device might fail EMC. This is one reason that, even when cutting a design into two regions, fast digital signals on the digital region in the DGND region could still produce some excess radiated emissions.
@@Zachariah-Peterson Let me self-questioning my question. After watching the new episode of "Bridging Grounds with Ferrites? TERRIBLE IDEA!!!". It really solved my question.
Excellent Idea juss as said by Rick Hartley
Hi Zach! Thanks so much for this very valuable content. Great format, clean and concise explanations 👍🏻
I was wondering if you could cover analog and mixed-signal audio design/layout strategies in the future? I have noticed a lot of contradiction regarding guidelines online. Thanks !
Hello, sure I can put that into our list of upcoming videos, and yes there can be some contradictions in terms of layout guidelines.
What if the analog section and digital section are connected using cables? Do that also increase EMI?
i think you should use a coaxial cable, with the woven copper shield attached to the ground of the analog and digital sections.
I can't convince the company I'm at now to accept a one ground approach. The engineers insist on splitting planes and tying them together at an SPG point. Any suggestions for resources I can use to prove that the one ground approach is better?
Are they trying to route stuff over the gap between those plane regions, or do the components in each region stay in one area and do not require routing signals between them? If they are not routing any signals between the two regions or they are routing only across the region near the SPG then the board could technically work fine but it's more difficult to design. Maybe take a board that was built their way, place and route the same board without an SPG, and see if you can do it better and with less noise?
Thank you so much
You're most welcome
Hello Zach, I am designing an amplifier consisting of 3 or 4 high-speed Op-amps and in all of the datasheets it says that a window should be opened in the ground plane under the input and output pins, to minimize the capacitance. Does that also create return path and EMI problems? How do I deal with that?
I will just say that it depends, those inputs are high impedance, so the intention is to reduce the capacitive loading at the input pin. You can compare the capacitance on the input pin to the capacitance of the trace. The trace capacitance will be on the order of 3 pF/inch, whereas the op-amp input pin could range anywhere from sub-pF to high pF. If the input capacitance is large then the trace won't matter unless you have other reactive components in the feedback loop. The other thing that can happen with op-amps is that they exhibit an underdamped oscillation on the output when there is excess inductance in the feedback loop and excess capacitance at the summing node, but this is more of a problem when the gain bandwidth products are very high. What is the part number you are using?
Sometimes I feel guilty of not following the datasheet's recommendation of separating ground planes (which in the real world is sometimes impossible to do). Thanks for this, I've been doing it right all along, ha!
Thanx
Brilliant, Thank you :)
So does this mean I shouldn't even worry about distinguishing between AGND and DGND? They should both just immediately connect to the single, main ground plane?
You should not worry about distinguishing between AGND and DGND except in an isolated ADC or some other isolated component. In an ADC or DAC these will be connected together on the component die. As far as routing is concerned to impact return paths, when in the audio range it can help to intentionally route the ground for a signal alognside the trace, or use a differential pair. But this is not the same thing as using separate ground regions.
What if your boards are small enough that the end of the gaussian distribution is coming over the analog part of the board. How do you layout then?
Route things on opposite surface layers, or put some routing on internal layers. As you get small your layer count tends to go up because, at some point, that is the only way to fit traces into the PCB. Also you can reduce layer thickness while keeping the spacing between nets constant, this will always help reduce crosstalk.
Thank you for these explanations but lots of manufacturers' application notes recommend 2 ground regions for example for signal buffering IC's on the internet. They recommend 2 ground regions : one on the left small signal input section of the IC and another region on the right output side . However they all also show a thin connection to the 2 grounds. So kindly how do you explain that?
Hello IHT sarl, What you just described is a lot like a star ground and it's a typical recommendation you will see for some signal interface ICs. Two examples that come to mind are interface converters (like SPI to I2C, etc.), level converters, and ADCs. In what you described, the grounds are being connected at some point so both regions will have the same potential. This is often recommended for isolation because the IC manufacturer is trying to help you prevent signals on the IOs from interfering. The problem with it is that you can only route other signals over the continuous ground section without creating an EMI source, so it makes correct routing more difficult. In the case of an ADC, the pin naming might convince you to try something similar, but I've seen an Analog Devices note that better explains this and states explicitly the various DGND and AGND pins should be tied together externally.
I think most designers that deal with a lot of EMI problems will agree that application notes should sometimes be viewed with suspicion, or the recommendation should at least be tested first. Just be careful about blindly following application notes and reference designs, because the recommendations might not always be best for your specific system. It's one thing if you are just replicating their test board or evaluation product, it's totally different if you are designing a custom board or adding to an existing board.
amazing video. thank you. I have a question. Recently i was designing a part of Li-ion charging . in that part i used a chip MAX8724 . surprising fact that i have found split ground place for PGND and GND in their Evaluation kit. it was a 6 layer board. could you please explain that why is that split ground was done? Normally i use solid GND place and use different blocks in different regions just as you shown. but after building the circuit in my way it didn't work . what could be the possible reasons for that? again, thank you very much for what you are doing for us.
If you look at the datasheet for the MAX8724, you'll see that they do connect those grounds together. I'll make a video of this showing how to do it.
The answer is on page 16 of the datasheet. You'll notice that they connected PGND and GND right by the battery. So they are designed with a single GND net, just not a large plane everywhere. You would want to use a net tie to make that connection right by the battery connector.
Using a full ground plane, do you recommend using the AC (120volts) on 1 layer (Top), gnd layer (middle), and digital layer (bottom). To separate the signals with a ground layer?
@Phạm Chiến Trung I’ve also seen that, my issue is the pcb convert AC to 12v 5V and 3v. With that I use moc3083 to switch ac power going to lamp ballast. So I need all in one board :-$
we connected two ground planes through a capacitor as Y capacitor ,will it create a problem in the EMI/EMC testing
I'm going to assume this was done in an isolated DC/DC converter, because the standard guidance is to use a Y-type safety capacitor in order to maintain the galvanic isolation at DC. This generally does not create a radiated EMI problem as long as signals originating on the secondary side of your DC/DC converter are not routed over to the primary side. This includes any feedback signal, which needs to come back to the switching driver on the primary side using an optocoupler. The only potential EMI/EMC problem is leakage current through the Y-type capacitor and onto any connectors or terminals, some industry specific EMC standards (e.g., medical) have very low leakage current requirements and it might be difficult to find a capacitor that offers the high voltage rating and low leakage in the right capacitor values.
Can we have a details demonstration video regarding all the possible scenarios of EMI issues in a PCB and current EMC checking process that an industry follows and minimum guidelines have to be met to make a product released in market?
That will probably take a series of videos, we've covered some of those topics in the past but we will try to do more of these.
So if I have IIC devices on 2 different board (with different GND plane) . Is it Ok to just connect them by a 2 pin cable ? (SDA/sCLK), is that one of typical scenario you don’t know where the return path is and there would be EMI problem?
Best practice is to use a 3-pin connector that includes a ground trace, especially if there is no reason to keep the grounds fully isolated. Just connect the GNDs with the GND wire.
For a mix signal system with 0-5V power rail, 2.5V reference, would the signal return path be in the 2.5V reference plane? How to hand this "virtual ground"?
Hey Zach, thanks for the really informative video. I was wondering though, if you route the (DC) power supply in a U shape around some Digital or Analogue sections of your PCB to supply some components on the other side of the board, wouldn't it be advisable to route the GND (so the return path) for that DC power supply also in a U shape? Because with the Low frequency of the DC Power supply the return current would not travel underneath the forward path but rather take the shortest way back, and interfere with those of my components placed inside U shaped Trace right? Greetings, David
If you happened to route DC in a U shape and you wanted a return path to follow the same shape, then you would want to also shape the returning conductor into a U shape. I wasn't trying to say that any kind of U shape route is how this will turn out in reality or that you will always do this, it is meant to be a simple example. But you are correct that the DC return won't follow the power conductor, for truly DC power this occurs because the return current is not being induced capacitively into the return conductor.
I'm a ECE student and design hardware.
In my recent project, I designed an ESP32 based LoRa Sx1276 where I had to use the SX1276 chip instead of Ready made SoC module.
What I did is just separated the LoRa Section and Placed Via Fence around. I created GND plane for rest of the PCB but left the LoRa section.
Is this approach legit?
Thanks
It sounds like you made the right approach, but I don't like to make promises unless I can see the layout. If you want, you can send me a private message.
Sometimes you have a very small board where you have to pack several analog channels and the corresponding digital section to control and capture these analog signals. In this case you don't have space to really separate analog from digital. When this happens, it is ok to split the planes, even create GND plane "sections" for each analog channel using keepout lines in order to contain the fields
The important thing, as you mention, is to make sure you absolutely don't route over the slots and you have a clear an uninterrupted return path for all your signals. You will have this "bridge" of continuous GND plane for the tracks interfacing the digital and analog sections but each analog section will have its own GND plane section created using keepout lines.
Manuel, I totally agree, it's appropriate to make the split in certain situations. In some cases it's even preferable. The point about return path is critical and so many people get in trouble with this, so I find it's best for some designers to do the safe thing and just use a plane layer to provide the return path.
I don't see how it would be preferable in that case to split the ground plane. Wouldn't it be better in that case to keep a continuous ground and use a via wall between analog and digital?
I think the only use case of split ground is when you have galvanically isolated sections that only commumicate or exchange power via optocouplers or transformers, capacitors or some other means.
Why don't you just use a Wire to connect to two or more isolated GND planes on the same PCB circuit? I see a lot of companies like TI use this kind of method when they have an isolated GND planes on their boards.
My whole life is a lie
🤣
Hi...your videos really helpful
That you mentioned in video use same gnd uniformly on both analog and digital..but is it good pratice to give analog gnd(gnd present in analog circuit) under digital gnd plane @Zachariah Peterson