Hey Zach, thank you so much for sharing your wealth of knowledge with future designers like myself. This information is extremely valuable and I know it will really give me a leg up going into the PCB design world. Also, thank you so much for explaining it in a very clear and concise manner with visuals, because many teachers and TH-camrs fail to do that. God bless!
What do you suggest about powering motors/cooling fans? I find that shared GND planes with motors/cooling fans induce small noise/spikes to the rest of the system. Having a dedicated GND return path for the motor/cooling fan helps eliminate/isolate the noise spikes from affecting rest of main system.
I still don't see what's wrong with doing both. When I do a mixed signal design, I still isolate Digital and Analog through careful placement, but I still like to carve out the grounds, or rather, place analog AGND Islands that are still connected to the DGND (usually with a large net tie) underneath or near the ADC/DAC (digital/analog) boundary. If all digital signals are routed over top of the DGND and all analog signals are routed over the AGND, and if those 2 GNDs are tied together at the MCU ADC or DAC where A&D meet, then what is wrong with that? I still ensure current steering, where no digital GND currents can get into AGND, sections and add noise to sensitive analog signals.
Hey Man! Would like to give a big shout ! Hip hop hurrah your videos are just awesome and so informative gained in-depth knowledge looking forward to more about HDI interconnect and blin buried vias
Do you recommend using the AC (120volts) on 1 layer (Top), gnd layer (middle), and digital layer (bottom). To separate the signals with a ground layer?
Hi Lee, you would want to try and segment the rails so that you are getting power to different regions of the board based on where your groups of components are located. This can be tricky because, sometimes, you have multiple levels operating within a specific group of components. Other times, you might have a single component that needs multiple levels (for example, large processors or BGA components/FPGAs). I would try and do it all on one layer if possible. I'll ask one of the internal Altium guys to set up a tutorial showing how to do it in an example layout.
@@Zachariah-Peterson Hi Zachariah, thank you for your reply very much appreciated and extremely useful as I'm currently working on a design containing BGA's and an FPGA.
They do, they're both analog signals and they can interfere with each other. If they are at different frequencies on different interconnects, filtering is usually used to eliminate one of the frequencies from entering a component where it isn't wanted. If they have to occupy the same interconnect on a receiving element, it's more challenging when two signals coexist. Just as an example, signals in the ISM band can interfere with each other due to coexistence in overlapping frequency ranges, so filtering or time division multiplexing would be needed to separate these. In a PCB layout, we try to route different signals things in perpendicular directions and place lots of shielding around these interconnects where possible to prevent the electromagnetic field of one signal from reaching into the interconnect of a different signal. The same ideas apply in suppressing analog from digital, however filtering cannot be used with digital signals because they are wideband and a filter would distort a digital signal.
Hy! great video, however I have some questions :) I'm planning to do a DC Load (MOSFET's controlled by an opamp, which driven by a DAC, and also 2 ADC (one measure the voltage across the loaded circuit, and the other will measure the voltage on a shunt resistor, which between the FET's and the ground) The MCU will be an ESP32, which will have an RTC/LCD/buttons/rotary encoder/keypad/temperature sensor too. The DAC uses SPI, and the ADC uses i2c bus. There are also a -5V generator (from the 5V rail) with ICL7660 which needed. So the main question is: what If I do the FET/DAC/ADC stuff in one board (without any digital) and the I2C and SPI bus will have pin headers, which connects to an another board, where the MCU, and the other periferials connected (RTC/buttons/LCD/etc) Of course, the SPI/I2C bus connector will have a ground wire, and the digital connector from the DAC (or ADC) will not so far away... Does this kind of modular setup can work? What kind of connector/cable should I use, if I do this? Thanks, Peter
For I2C or SPI a short SWD connector with a ribbon cable is usually fine. If you look at some programmers (like FORTE), they are basically using SPI over a ribbon cable or a set of flying leads and those at least funciton. I would look at the pinout on the cable and make sure you can through in some ground lines.
Great video! I have a quick question about the via fencing however. From what I understand they are used to provide a lower impedance path for return currents as well as isolating noise from high frequency lines/traces. In that case, why not just use a ground pour on the top layer? To clarify, I typically work with 2-layer PCBs as we have very few components and so we do not need all the layers. Saying that, if I were to create a ground pour in-between all the components on the top layer, and a complete ground pour on the bottom layer, would this be better than using the via fencing?
Hi Luke, sorry for missing this comment, but we just did a video that talks about this, you can watch it here: th-cam.com/video/R3w4Go1s1hM/w-d-xo.html Copper pour is a complex issue that is sometimes poorly communicated. You can use it to suppress RFI, but only if it is designed correctly. For a 2-layer board, copper pour might be one of the few ways you can get some easy access to ground without routing a bunch of extra traces, so it's understandable that it gets used in those instances. If you are going to use copper pour in the way you describe, then it would be best to use it with some via stitching around the top layer so that you can get some EMI benefit and to make sure you get plenty of good return paths back to GND as you suggest.
EMI/EMC specialists, PCB fabs, component vendors and engineers seems to have their own ideas, leaving PCB designers much in limbo who to listen to and then just base on experience of trial and error for passing in the EMI lab without a good clue why exactly it passed (or failed).... it's called dark magic / art. There are so many don't and no's that often you end up without any practical solution, at least some violations or a high count layer board. I did it the other way around as the ADC location and all analog connectors could not change position on the board.. after that find a place for the MCU and digital parts using one solid shared ground plane but separated 3V/5V/9V power area's on the power plane. For signal traces next to the power plane it was sometimes impossible to avoid crossing power area's or having via's, For analog/digital separation followed the 20H rule. Also some components use 9V/5V/3V dual power.Think about SPI/I2C voltage translators referencing which power plane ?. .Would like some advise here. until then, keep fingers crossed if the "work of art" will work. :-) also a question on these isolation via's as at high frequencies the return is under the traces and won't spread, then why the via's ?
Analog devices and TI guidelines priorities simplicity and reliability over EMI. In this instance AD recommends cut ground planes for control circuitry in switching power supplies. Because power supplies produce the interference of a digital system with the sensitivity of an analog one, these are usually the most layout intensive after RF.
Which design guidelines or application note? I've read two of their design guidelines, one that says to split the planes around an ADC and another that says it's not necessary. I've even an AD app note that recommends star grounding, which is a terrible practice for just about everything except DC. @LightningHelix01 is correct, they have traditionally prioritized simplicity and, as a result, the app note writer tends to regurgitate old design guidelines just because they worked in the past (when chips were slower and analog frequencies were lower). The result is that old guidelines get repeated over and over, and of course the semiconductor companies can't be held responsible if you follow their guidelines and the board doesn't work or pass EMC testing. You can usually tell if the layout guidelines are outdated just by looking at the date on the app note. If the app note is from 15+ years ago, you probably shouldn't follow it. Just a note, there are instances where you should split planes, but this is the exception, not the rule. Trying to isolate digital signals from analog signals is not one of those instances. Two examples where it's required or appropriate to split are isolated power supplies and high fidelity audio because the frequencies involved are low, so it's hard to control the return paths without splitting planes or routing dedicated ground traces. In isolated power supplies or transformer-coupled systems, this is done for galvanic isolation. It's even appropriate in power over Ethernet, which uses transformer-coupled termination, in order to hit the ESD protection requirements in the 802.3af standard.
man these videos are more useful than 4 years at university
🤣
Hey Zach, thank you so much for sharing your wealth of knowledge with future designers like myself. This information is extremely valuable and I know it will really give me a leg up going into the PCB design world. Also, thank you so much for explaining it in a very clear and concise manner with visuals, because many teachers and TH-camrs fail to do that. God bless!
Great tutorial; feeding the alg! ;) Well done.
What do you suggest about powering motors/cooling fans? I find that shared GND planes with motors/cooling fans induce small noise/spikes to the rest of the system. Having a dedicated GND return path for the motor/cooling fan helps eliminate/isolate the noise spikes from affecting rest of main system.
It was really helpful specially Coplanar Waveguide Routing
A fluid narrative
he's great, i'd love to see some practical design lessons from him.
I'll be doing something more practical with USB and Ethernet coming up, stay tuned!
Thank you so much ❤
*_Thanks a lot, it was educational!_*
I still don't see what's wrong with doing both. When I do a mixed signal design, I still isolate Digital and Analog through careful placement, but I still like to carve out the grounds, or rather, place analog AGND Islands that are still connected to the DGND (usually with a large net tie) underneath or near the ADC/DAC (digital/analog) boundary. If all digital signals are routed over top of the DGND and all analog signals are routed over the AGND, and if those 2 GNDs are tied together at the MCU ADC or DAC where A&D meet, then what is wrong with that?
I still ensure current steering, where no digital GND currents can get into AGND, sections and add noise to sensitive analog signals.
Hey Man! Would like to give a big shout ! Hip hop hurrah your videos are just awesome and so informative gained in-depth knowledge looking forward to more about HDI interconnect and blin buried vias
really informative
please consider high voltage high current switching power supply layouts review in future videos esp. isolated ones
Noted
Hello via pense without top layer ground connection is not working. Do you know any reason?
Thanks☺️
Welcome 😊
Do you recommend using the AC (120volts) on 1 layer (Top), gnd layer (middle), and digital layer (bottom). To separate the signals with a ground layer?
Brilliant thank you, how would you segment the power plane on a mixed signal board?
Hi Lee, you would want to try and segment the rails so that you are getting power to different regions of the board based on where your groups of components are located. This can be tricky because, sometimes, you have multiple levels operating within a specific group of components. Other times, you might have a single component that needs multiple levels (for example, large processors or BGA components/FPGAs). I would try and do it all on one layer if possible. I'll ask one of the internal Altium guys to set up a tutorial showing how to do it in an example layout.
@@Zachariah-Peterson Hi Zachariah, thank you for your reply very much appreciated and extremely useful as I'm currently working on a design containing BGA's and an FPGA.
Why don't analog signals and RF signals interfere with each other?
They do, they're both analog signals and they can interfere with each other. If they are at different frequencies on different interconnects, filtering is usually used to eliminate one of the frequencies from entering a component where it isn't wanted. If they have to occupy the same interconnect on a receiving element, it's more challenging when two signals coexist. Just as an example, signals in the ISM band can interfere with each other due to coexistence in overlapping frequency ranges, so filtering or time division multiplexing would be needed to separate these. In a PCB layout, we try to route different signals things in perpendicular directions and place lots of shielding around these interconnects where possible to prevent the electromagnetic field of one signal from reaching into the interconnect of a different signal. The same ideas apply in suppressing analog from digital, however filtering cannot be used with digital signals because they are wideband and a filter would distort a digital signal.
Hy! great video, however I have some questions :)
I'm planning to do a DC Load (MOSFET's controlled by an opamp, which driven by a DAC, and also 2 ADC (one measure the voltage across the loaded circuit, and the other will measure the voltage on a shunt resistor, which between the FET's and the ground)
The MCU will be an ESP32, which will have an RTC/LCD/buttons/rotary encoder/keypad/temperature sensor too.
The DAC uses SPI, and the ADC uses i2c bus. There are also a -5V generator (from the 5V rail) with ICL7660 which needed.
So the main question is: what If I do the FET/DAC/ADC stuff in one board (without any digital) and the I2C and SPI bus will have pin headers, which connects to an another board, where the MCU, and the other periferials connected (RTC/buttons/LCD/etc) Of course, the SPI/I2C bus connector will have a ground wire, and the digital connector from the DAC (or ADC) will not so far away... Does this kind of modular setup can work? What kind of connector/cable should I use, if I do this?
Thanks,
Peter
For I2C or SPI a short SWD connector with a ribbon cable is usually fine. If you look at some programmers (like FORTE), they are basically using SPI over a ribbon cable or a set of flying leads and those at least funciton. I would look at the pinout on the cable and make sure you can through in some ground lines.
Great video! I have a quick question about the via fencing however. From what I understand they are used to provide a lower impedance path for return currents as well as isolating noise from high frequency lines/traces. In that case, why not just use a ground pour on the top layer? To clarify, I typically work with 2-layer PCBs as we have very few components and so we do not need all the layers. Saying that, if I were to create a ground pour in-between all the components on the top layer, and a complete ground pour on the bottom layer, would this be better than using the via fencing?
Hi Luke, sorry for missing this comment, but we just did a video that talks about this, you can watch it here: th-cam.com/video/R3w4Go1s1hM/w-d-xo.html
Copper pour is a complex issue that is sometimes poorly communicated. You can use it to suppress RFI, but only if it is designed correctly. For a 2-layer board, copper pour might be one of the few ways you can get some easy access to ground without routing a bunch of extra traces, so it's understandable that it gets used in those instances. If you are going to use copper pour in the way you describe, then it would be best to use it with some via stitching around the top layer so that you can get some EMI benefit and to make sure you get plenty of good return paths back to GND as you suggest.
Now I'm confused. Design guidelines from Analog Devices says to split planes. You said No. Haha. What should we follow?
EMI/EMC specialists, PCB fabs, component vendors and engineers seems to have their own ideas, leaving PCB designers much in limbo who to listen to and then just base on experience of trial and error for passing in the EMI lab without a good clue why exactly it passed (or failed).... it's called dark magic / art. There are so many don't and no's that often you end up without any practical solution, at least some violations or a high count layer board. I did it the other way around as the ADC location and all analog connectors could not change position on the board.. after that find a place for the MCU and digital parts using one solid shared ground plane but separated 3V/5V/9V power area's on the power plane. For signal traces next to the power plane it was sometimes impossible to avoid crossing power area's or having via's, For analog/digital separation followed the 20H rule. Also some components use 9V/5V/3V dual power.Think about SPI/I2C voltage translators referencing which power plane ?. .Would like some advise here. until then, keep fingers crossed if the "work of art" will work. :-) also a question on these isolation via's as at high frequencies the return is under the traces and won't spread, then why the via's ?
Analog devices and TI guidelines priorities simplicity and reliability over EMI. In this instance AD recommends cut ground planes for control circuitry in switching power supplies. Because power supplies produce the interference of a digital system with the sensitivity of an analog one, these are usually the most layout intensive after RF.
@@LightningHelix101 Copy that
@@rajimordecai1099 good luck!
Which design guidelines or application note? I've read two of their design guidelines, one that says to split the planes around an ADC and another that says it's not necessary. I've even an AD app note that recommends star grounding, which is a terrible practice for just about everything except DC.
@LightningHelix01 is correct, they have traditionally prioritized simplicity and, as a result, the app note writer tends to regurgitate old design guidelines just because they worked in the past (when chips were slower and analog frequencies were lower). The result is that old guidelines get repeated over and over, and of course the semiconductor companies can't be held responsible if you follow their guidelines and the board doesn't work or pass EMC testing. You can usually tell if the layout guidelines are outdated just by looking at the date on the app note. If the app note is from 15+ years ago, you probably shouldn't follow it.
Just a note, there are instances where you should split planes, but this is the exception, not the rule. Trying to isolate digital signals from analog signals is not one of those instances. Two examples where it's required or appropriate to split are isolated power supplies and high fidelity audio because the frequencies involved are low, so it's hard to control the return paths without splitting planes or routing dedicated ground traces. In isolated power supplies or transformer-coupled systems, this is done for galvanic isolation. It's even appropriate in power over Ethernet, which uses transformer-coupled termination, in order to hit the ESD protection requirements in the 802.3af standard.
great video
I have doubts regarding RF path shown in this video... (For be sure would be nice to see schematic..)
Still I am not clear about solution
cool
Very nice explaination!!! You considered ny request!
great to see!
everything is fine except the annoying music.