@3:42 you say 400 micron but it is actually 0.4 micron or 400nm. Then you say @4:00 gate length is 0.4 micron which is wrong as well, because the gate length is 0.06 micron.
@@analoglayout the gate length should be .06um, not .4um. Gate length is measured from poly edge to poly edge. I think you're confusing gate length for gate width.
Do we have any strict rule that interdigitization pattern is only used for current mirror and common centroid pattern for differential pair?if yes/no why?
May I know what is the difference between one transistor 400um with 2 fingers and two transfer 200nm multiplier......(in this case both are same or not???)..and how fingering used for IR and multiplier is for current can u elaborate......???
Sir i have a doubt please clarify anyone if device 'A' having 1600nm width four fingered device and device 'B' having 400nm width with multiplier 4 what is the difference between them when sharing of source and drains of multiplier device 'B' thanks in advance
Thank you! Someone finally explained it!
short and clear.....loved it
when you select the devices in layout it got highlighted in schematic, how to enable that option in cadence?
Use virtuoso XL and schematic XL
@3:42 you say 400 micron but it is actually 0.4 micron or 400nm. Then you say @4:00 gate length is 0.4 micron which is wrong as well, because the gate length is 0.06 micron.
thanks for this info
its a good information about multiplier and finger,,,,,,,now i got the exact concept....and tnq for for giving such information.
Superb explanation. Thank you soo much. Now I got clear idea about fingers and multipliers.
7:34 why did you say overall width of transistor remains same? in the two finger isn't transistor width 200nm for both transistors?
Nice video sir.but a small mistake....gate length is not 400nm it is 60nm.....
Thanks for ur videos..... Please make videos about skill code
in which way your saying this is 400nm ???? i have pdk with 65nm and 60 nm tsmc ???
@@analoglayout the gate length should be .06um, not .4um. Gate length is measured from poly edge to poly edge. I think you're confusing gate length for gate width.
@@thiluong6678 yeah i also think the same
Do we have any strict rule that interdigitization pattern is only used for current mirror and common centroid pattern for differential pair?if yes/no why?
no rules , only pattern we have to follow
Good video useful one.
I like your channel
thx for your support
What is the short cut for parameters in sch. Can you please explain how to use tool bro.🙂
love it
Suppose I have set m=2 and cadence operating point table shows a gm = 100.
Is this the gm of a single MOS or the two MOS combined?
May I know what is the difference between one transistor 400um with 2 fingers and two transfer 200nm multiplier......(in this case both are same or not???)..and how fingering used for IR and multiplier is for current can u elaborate......???
Sir i have a doubt please clarify anyone if device 'A' having 1600nm width four fingered device and device 'B' having 400nm width with multiplier 4 what is the difference between them when sharing of source and drains of multiplier device 'B' thanks in advance
Tell me about matching pattern for current mirror and differential pair each having more than 10 multiplier?
this Sunday , i will upload full layout for diff pair and current mirror
gate length is 60 nm
which is wrongly mentioned !
Thanks for the notice
Thanks
Also, different PDKs will interpret fingers and multipliers differently. in might be one way in tsmcn65, another way in GF180.