Hi Sir , I am facing exactly same issue while performing LVS on 12nm tsmc finfet design , but i dont know whats the name of layer to add, can you help me in this regard ?
In samsung foundry what is the name of this layer? Or any alternate layer are present Im facing 2 different vss i need to isolate one of the vss how to do?
@@analoglayout so at that time when we are doing placement right at that time only we need to take care.when we saw two separate bulks means we need to keep instance with sepate and minimum DRCD spacing
Thanks for restarting the channel, i mean after so many days a new video uploaded in this channel
Not date's, it's almost 13 months - no videos, here on regularly videos will be uploaded
@@analoglayout thank you so much
Hi Sir , I am facing exactly same issue while performing LVS on 12nm tsmc finfet design , but i dont know whats the name of layer to add, can you help me in this regard ?
All the tsmc foundry have same name, psub2 layer, but before adding this layer consult with your senior person
Thank u for continuing your videos
Thanks for the video, it helped me out!
In samsung foundry what is the name of this layer?
Or any alternate layer are present
Im facing 2 different vss i need to isolate one of the vss how to do?
Go for dnw - don't use psub2 layer, because this will not actually isolate the gnd, just for the lvs we are using this
sir how can I download TSMC library pdk?
Could you please suggest?
Impossible to get tsmc pdk from outside, even to get this legally is very hard
Good explanation
Hi sir I have doubts which one i need to take supporter or navigator
You can be a supporter in youtube, but I'm not able to provided any additional training in the other membership.
At that time we need to maintain spacing between these two instances right.otherwise we will get base DRCD
No need to maintain od spacing, you can merge the od , how ever it's gng to connect to the same signal in the top level
@@analoglayout in 3nm of must continue but what am trying to say is we need to keep dummy in between also but substrate itself will get short right
@@SASIDHAR-ol8ej depends on the connection
@@analoglayout so at that time when we are doing placement right at that time only we need to take care.when we saw two separate bulks means we need to keep instance with sepate and minimum DRCD spacing