What is a Latch in an FPGA?

Latches are bad! Learn how a latch gets created in VHDL or Verilog and how to therefore avoid creating them. SR, D, JK, Earle, these are all latches that serve no purpose in modern FPGA design, so avoid them at all costs.
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[@mikal_1]

"first of all my name is Russel." lmao nice

[@siyavashadib9067]

Hey Dear,
Really happy to see you again . I've used to learn so much from you when you were posting those FPGA tutorials in the past . Now i'm so happy to see you posting new ones that I can learn from . Keep up the good work . Thanks a lot for all the good content .

[@xXernendeRXx]

Thank you for this on point video, the amount of information and the way you share it is amazing and really life saving.

[@curtisnotestine3134]

Could you write " else o_latch

[@izobretate]

That's the perfect way to keep the latch alive) if you want to get rid of it you shouldn't do it.

[@isaiahgarcia3951]

I never comment on TH-cam videos but I need to say, You sir have saved me from effing up my lab , thank you.

[@AxElKo440]

Love this explanation. Thank you :)

[@netbust3r]

the comeback!!

[@larsbrinkhoff]

I feel safe ordering a product from another Emacs user. Thanks.

[@Nandland]

haha

[@duality4y]

latches are interesting to learn about and the are the fundamental building blocks of a flipflop

[@jackyo8547]

Hi there,
If I would like to use latch to store clock frequency and display it. how would I do that? any videos out there talking about it? thank you

[@powerforceforce2793]

Hey I have a dashboard that I found in my work but I do not understand I can send you a photo? could you help me???

[@powerforceforce2793]

I also have AT89C5RD2-A 1127 THAT BRINGS A TIMER AND A ROSH HAVE PRINTS PL1, PL2, PL4, PLA ,,, PL OPCION B ... PLEASE HELP ME ??? Yesterday I was watching one of your videos !!!

[@akpresentations3645]

If I need to detect a pulse on sdata when sclk is turned off in a serial interface, how to do so without using a latch?

[@anthonyrocha8075]

Mr NandLand is a good nickname.

[@Btw_visit_____todacarne-com]

Hey Russell, have you ever designed a completely asynchronous circuit (no clock)? NO ? Maybe that is why you have not needed latches.
Async circuits are the future (scalability, reliability, speed). We need hardware that CAN do asynchronous circuits.

[@paulmichael3694]

This video is fantastic

[@TooSlowTube]

2/3 of the way through, and I'm bothered that the example of how to solve the problem does something different than the code which it's supposed to be fixing.
In the original, o_latch kept its value unless i_enable was 1. In the "fixed" version, it was set to zero if i_enable was zero. So, the "fix" is to make the circuit do something different, not just to make the circuit in a different way.
I have real trouble getting past this kind of thing.
Also, what was so bad about latching data? That's what a register does. What's supposed to be so wrong with doing that?

[@xmotoFF]

Awesome! NANDLAND returns! Just one minor nitpick, your facecam is covering some words of the presentation, you might want to reposition it.

[@dmitr8194]

Did you design custom ICE40 HX1K FPGA board?

[@Nandland]

The Go Board! www.nandland.com/goboard/introduction.html

[@JoshSideris]

This video is a lot more interesting than the title lets on.

[@Nandland]

+Josh Sideris lol

[@rjstoneus]

Will synthesis/mapping try to construct latches out of two LUTs or other primitives? Yea that sounds bad considering that FFs exist for this purpose and are hard primitives.

[@taekwondotime]

*Latches are taught to students in digital logic courses because they are the fundamental buildings blocks upon which flip flops are built* . You can't understand flip flops without first understanding latches and the limitations of latches.

[@Nandland]

I disagree. Digital logic courses teach Karnaugh maps and DeMorgan's theorem too. I've used those in my professional career literally 0 times. They don't help design FPGAs at all. Latches at least you need to know what they are at a basic level so you know to never use them in FPGA design.

[@taekwondotime]

You may be right, but the thing is, it isn't enough for an engineer to be able to just use the existing technology. They have to know how it works and why they're using it instead of using something else.
What often happens is that people get accustomed to using something and they forget what they're doing or why they're doing it. That's why courses teach those fundamentals. It's so students understand what is going on "under the hood". :)

[@Nandland]

That's a good argument. My concern is when teachers get their students too buried in the details at the beginning. Students lose their ability to see the forest through the trees and lose interest in the subject. I saw it in my engineering classes over and over. It was interesting material, but not taught in the right order. My focus with nandland is starting with the fun stuff to get people making things quickly and if they want to dive deeper they can certainly do that.

[@HansBaier]

Would have been nice to get one example showing the evilness of latches in action. Otherwise great video!

[@chatgpt94274]

good

[@karamany9870]

Are FPGAs used a lot in defence?

[@wuxi8773]

VHDL, emacs, non-xilinx, must be a east coast guy

[@kellypainter7625]

emacs on windows!

[@Hfgh564]

Latches are evil...haha, I wish they teach it in university...