To divide by a number other than 2, you can multiply by its reciprocal to an arbitrary precision. For example, to divide by 3, you can multiply by 21845, then shift the result right by 16 bits, which divides by 65536. 21845/65536 is about 1/3. For a more precise result, use more bits!
@gautha pandith A binary multiply can be represented as a series of shifts and additions. Take for example 6 * 10, which in unsigned binary is 110b * 1010b. The multiplicand (6) is shifted based on the position of each 1 bit in the multiplier (10), and all of the shifted values are added together to get the result... (6
Appreciate the elaboration. When I took a digital design course in college, my professor didn't explain the SIgned and Unsigned stuff properly. Then again, I wasn't aware of FPGAs until my last semester in college. smh.
In the beginning, isn't what was explained as the two's compliment of 1 actually -1. This is going by another simple way to explain 2's compliment, which is to say that every bit is the weight of a power of 2, except for the most significant bit, which has a weight of the NEGATIVE of its respective power of 2.
You learn to add in 1st grade....many start in Kindergarten. I just ordered the Go Board - look forward to the lessons. Already watched most of the videos!
Excellent explanation. I just wondered how to divide with anything that 2,4,8 and so on. You gave me the coolest answer I ever heard - complicated. That is so true. Thanks. EDIT: Typo: should be ...anything than 2,4,8... that makes sentence different.
In general: ÷M = shift right by N bits, where M = 2^N. E.g. ÷4 = shift right by 2 bits, ÷8 = shift right by 3 bits, etc. To multiply by the same factors, just shift left by the required number of bits instead.
Hey Dear Russel , I'm one of the many people who used your tutorials on the GoBoard to learn a few things and take the first steps into the FPGA world . First I wanted to thank u for all the great help and guidance that actually helped me get my first Job related to FPGA development . I've been working on a more complex development board for myself with some more components like HDMI , MicroController and . . . But I can't figure out how to make a programmer on board using the FTDI chip like u did on the GoBoard in a way i can use it both for Serial interface and Programming the FPGA . I Would really appreciate it if u could give me a hand on this since I have almost no idea how to make one . Best Regards
Some FPGA boards just work with the FTDI chip, some don't. It depends on the FPGA. I'm not sure which ones do or do not work. The Go Board schematic is on this page: www.nandland.com/goboard/index.html Hope that helps. Good luck!
Thanks a lot , I've been searching about the FTDI's FT2232 and how to use it for this purpose but i can't figure out how to configure the EEPROM for the FTDI to enter the JTAG HS2 mode to program the FPGA . I Saw some Xilinx FPGA boards using this as well . Can u share the code of the EEPROM for the FTDI on the GoBoard ?
Ah , alright . Thanks a lot for ur response . if u happened to know anything about how to make the FTDI chip to act as a JTAG HS2 let me know please . Best Regards
Thanks for your work, man! Keep it up! Really keeps me motivated to spend my free time tinkering with FPGAs. By the way do you plan on covering fixed point arithmetic on an FPGA?
nandland great! Will be waiting for that one. Also I would be happy to see a video on how to _properly_ organize a device configuration (i2c sensor for example, a common case with dev boards) without any kind of system on chip.
Division is simple. division is subtraction with right shift divisor: 135/10=13 (%=5) -->> 135-("0"*'160')-("1"*'80')-("1"*'40')-("0"*'20')-("1"*'10') -->> Result="01101b"=13 Remainder=5
@@TEAbouda if 135>=(10 x 2e4) then multiplier is 1 else multiplier is 0 2e4 = 16 10 x 16 = 160 is not 135>=160 then multiplier is 0 (multiplier x 160) = (0 x 160) = 0 135 - (0 x 160) = 135 2e3 = 8 10 x 8 = 80 is 135>=80 then multiplier is 1 135 - (1 x 80) = 55 2e2 = 4 10 x 4 = 40 is 55>=40 then multiplier is 1 55 - (1 x 40) = 15 2e1 = 2 10 x 2 = 20 is not 15>=20 then multiplier is 0 (multiplier x 20) = (0 x 20) = 0 15 - (0 x 20) = 15 2e0 = 1 10 x 1 = 10 is 15>=10 then multiplier is 1 15 - (1 x 10) = 5 = remainder binary number 01101 is decimal 13
Speaking of integer division, it is slow on CPUs as well. When the divisor is known at design time, what compilers tend to do instead of dividing is a trick involving shifting, multiplying by some constant and then shifting again. The constant and shift amounts can be chosen in such a way as to get the same result as if division had been performed. Does anyone do this on FPGAs?
Regarding how one should use the verilog 'signed' and 'unsigned' keyword whenever comparing or doing math operations for synthesis (not simulation).. does the sign get extended automatically or does one need to do it manually? For example, would : reg signed [7:0] var; var
I have a question: typically when multiplying, the result will have a width equals to the total sum of the width of both factors. However i think that in signed multiplication it always end up with 1 extra bit which is the extended sign bit. Can we trunkcate this so the result could get better resource utilization?
You'll need to keep the "second sign bit" of the product only if you need to support multiplication of the largest negative value with the largest negative value. E.g., for 16-bit values, try to keep your data in the range [-32767,32767] instead of the maximum available range [-32768,32767]. The resource savings can be substantial.
Not in a symbolic way, and not with an arbitrary accuracy. An FPGA can do fast parallel integer operations at some user-defined accuracy, so you could just sweep the whole number area in a for loop and check if the current number is an approximate solution, but that's not an appropriate task for an FPGA.
Are you asking how the synthesis tool works? I'm sure you could read about different approaches to adding, multiplying etc in research papers and stuff. The actual implementation of the math is less important to me.
Hi, I've had a signed number problem alot lately. Sometimes either the compiler or (?) flips my number assignment, that is, for example, I declare a number as a signed number, but it treats it as an unsigned number, and vise versa. This problem comes and goes, so it's some sort of instability, but I can't seem to put a finger on it, and don't know how to fix it. Any encounter this before? Any help would be appreciated!
Why do you depend to continue making videos on the sales number of your board? Don't you have fun doing these videos in your free time to educate your viewers?
To divide by a number other than 2, you can multiply by its reciprocal to an arbitrary precision. For example, to divide by 3, you can multiply by 21845, then shift the result right by 16 bits, which divides by 65536. 21845/65536 is about 1/3. For a more precise result, use more bits!
Jeff, excellent point! I did neglect to talk about this trick. Darnit!
nandland no worries! Hope it's helpful to someone. Thanks for the videos!
@gautha pandith A binary multiply can be represented as a series of shifts and additions. Take for example 6 * 10, which in unsigned binary is 110b * 1010b. The multiplicand (6) is shifted based on the position of each 1 bit in the multiplier (10), and all of the shifted values are added together to get the result... (6
I need to do this to apply a low-pass filter on an image, and Vivado is complaining about a DSP not being pipelined. I don't know what that means.
Appreciate the elaboration. When I took a digital design course in college, my professor didn't explain the SIgned and Unsigned stuff properly. Then again, I wasn't aware of FPGAs until my last semester in college. smh.
In the beginning, isn't what was explained as the two's compliment of 1 actually -1.
This is going by another simple way to explain 2's compliment, which is to say that every bit is the weight of a power of 2, except for the most significant bit, which has a weight of the NEGATIVE of its respective power of 2.
You learn to add in 1st grade....many start in Kindergarten.
I just ordered the Go Board - look forward to the lessons. Already watched most of the videos!
Thanks for ordering! Glad you found the information useful!
Excellent explanation. I just wondered how to divide with anything that 2,4,8 and so on. You gave me the coolest answer I ever heard - complicated. That is so true. Thanks.
EDIT: Typo: should be ...anything than 2,4,8... that makes sentence different.
In general:
÷M = shift right by N bits, where M = 2^N.
E.g. ÷4 = shift right by 2 bits, ÷8 = shift right by 3 bits, etc.
To multiply by the same factors, just shift left by the required number of bits instead.
@@vk2ig Thanks. Okay, I made typo in my question. Should be: How to divide with anything than 2, 4, 8 and so on. This means dividing by 3, 5, 7 ...
@@MilanKarakas OK, understood. I have used the "shift left and subtract" algorithm to divide by non-integer powers of 2, but not on FPGAs.
@@vk2ig Thanks. I will figure out something. Just having pollen allergy... unable to do anything smart.
Awesome video! Definitely learned a lot from this, thank you.
Hey Dear Russel ,
I'm one of the many people who used your tutorials on the GoBoard to learn a few things and take the first steps into the FPGA world .
First I wanted to thank u for all the great help and guidance that actually helped me get my first Job related to FPGA development .
I've been working on a more complex development board for myself with some more components like HDMI , MicroController and . . .
But I can't figure out how to make a programmer on board using the FTDI chip like u did on the GoBoard in a way i can use it both for Serial interface and Programming the FPGA .
I Would really appreciate it if u could give me a hand on this since I have almost no idea how to make one .
Best Regards
Some FPGA boards just work with the FTDI chip, some don't. It depends on the FPGA. I'm not sure which ones do or do not work. The Go Board schematic is on this page: www.nandland.com/goboard/index.html Hope that helps. Good luck!
Thanks a lot , I've been searching about the FTDI's FT2232 and how to use it for this purpose but i can't figure out how to configure the EEPROM for the FTDI to enter the JTAG HS2 mode to program the FPGA . I Saw some Xilinx FPGA boards using this as well .
Can u share the code of the EEPROM for the FTDI on the GoBoard ?
For the Go Board I didn't have to do anything to the EEPROM. The Lattice toolchain is able to make it work. Sorry.
Ah , alright . Thanks a lot for ur response . if u happened to know anything about how to make the FTDI chip to act as a JTAG HS2 let me know please .
Best Regards
Thanks for your work, man! Keep it up! Really keeps me motivated to spend my free time tinkering with FPGAs. By the way do you plan on covering fixed point arithmetic on an FPGA?
Yes. Originally I planned to do it in this video, but it was already too long.
nandland great! Will be waiting for that one. Also I would be happy to see a video on how to _properly_ organize a device configuration (i2c sensor for example, a common case with dev boards) without any kind of system on chip.
Thanks for the suggestion, I'll add it to the list!
Hello, awesome video honestly, can you make a video with Time to digital convertor explained and ring oscillator explained
I'd like to know what happens when you assign an output as X in a case for don't care values
Very well explained! Thanks alot.
Great video, helped me a lot!
Division is simple. division is subtraction with right shift divisor: 135/10=13 (%=5) -->> 135-("0"*'160')-("1"*'80')-("1"*'40')-("0"*'20')-("1"*'10') -->> Result="01101b"=13 Remainder=5
Can you explain that more please?
@@TEAbouda if 135>=(10 x 2e4) then multiplier is 1 else multiplier is 0
2e4 = 16
10 x 16 = 160
is not 135>=160 then multiplier is 0
(multiplier x 160) = (0 x 160) = 0
135 - (0 x 160) = 135
2e3 = 8
10 x 8 = 80
is 135>=80 then multiplier is 1
135 - (1 x 80) = 55
2e2 = 4
10 x 4 = 40
is 55>=40 then multiplier is 1
55 - (1 x 40) = 15
2e1 = 2
10 x 2 = 20
is not 15>=20 then multiplier is 0
(multiplier x 20) = (0 x 20) = 0
15 - (0 x 20) = 15
2e0 = 1
10 x 1 = 10
is 15>=10 then multiplier is 1
15 - (1 x 10) = 5 = remainder
binary number 01101 is decimal 13
How to perform fixed-point addition in verilog?
Speaking of integer division, it is slow on CPUs as well. When the divisor is known at design time, what compilers tend to do instead of dividing is a trick involving shifting, multiplying by some constant and then shifting again. The constant and shift amounts can be chosen in such a way as to get the same result as if division had been performed. Does anyone do this on FPGAs?
Veeeeeeeeeeeeeeerrrrrrrrrrrrrrrrrrrry nice video for VHDL，thanks ，man。
Regarding how one should use the verilog 'signed' and 'unsigned' keyword whenever comparing or doing math operations for synthesis (not simulation).. does the sign get extended automatically or does one need to do it manually? For example, would :
reg signed [7:0] var;
var
Any idea why the last comparison fails? www.edaplayground.com/x/5g99
after addding 1 how did it go to 1010?
Hi! Thanks for your work! How to implement multiplication on FPGA when there is an arbitrary number of inputs? Is there a way to do so?
Is your Go Board still available for purchase? I am unable to reach the sales page.. Thanks!
I have a question: typically when multiplying, the result will have a width equals to the total sum of the width of both factors. However i think that in signed multiplication it always end up with 1 extra bit which is the extended sign bit. Can we trunkcate this so the result could get better resource utilization?
Sure if you really need the extra space. I usually don't bother.
You'll need to keep the "second sign bit" of the product only if you need to support multiplication of the largest negative value with the largest negative value.
E.g., for 16-bit values, try to keep your data in the range [-32767,32767] instead of the maximum available range [-32768,32767]. The resource savings can be substantial.
Is there is way to solve polynomial functions using Verilog on a FPGA?
Not in a symbolic way, and not with an arbitrary accuracy. An FPGA can do fast parallel integer operations at some user-defined accuracy, so you could just sweep the whole number area in a for loop and check if the current number is an approximate solution, but that's not an appropriate task for an FPGA.
u dont have to use 2s complement, but i probably will. do it however u wish.
But all that is like high level VHDL, what happents in real life? Behind the plus sign vhdl creates all the full adders or what?
Are you asking how the synthesis tool works? I'm sure you could read about different approaches to adding, multiplying etc in research papers and stuff. The actual implementation of the math is less important to me.
I dont think I have ever seen such a small whiteboard lol
Hi, I've had a signed number problem alot lately. Sometimes either the compiler or (?) flips my number assignment, that is, for example, I declare a number as a signed number, but it treats it as an unsigned number, and vise versa. This problem comes and goes, so it's some sort of instability, but I can't seem to put a finger on it, and don't know how to fix it. Any encounter this before? Any help would be appreciated!
Why do you depend to continue making videos on the sales number of your board? Don't you have fun doing these videos in your free time to educate your viewers?