Part 2: TSMC65nm Technology Layout | CMOS inverter Layout | Cadence Virtuoso

[@amitkumar-sh2lk]

love u bro from iitb

[@VLSIToolBox]

thank you

[@bvrao3323]

Good initiative sir. ....

[@VLSIToolBox]

Thank you keep watching

[@RohitKumar-me8fq]

where is ur pins in out gnd and vdd

[@VLSIToolBox]

it is there we check it..., VIN,VOUT, VDD, GND ports are marked.

[@Rohit_Magahiya]

@@VLSIToolBox but u did generated it from source right .....while I'm doing generate all from source pins are also coming in red....

[@VLSIToolBox]

ye i have not generated from source@@Rohit_Magahiya

[@VLSIToolBox]

you can also create pin later @@Rohit_Magahiya