Sir..my pre layout and post layout is mismatch. I tried inverter aslo.but pre layout & post layout mismatch. I am using SCL PDK. I don't know why it is coming like that
Yes you can have one source for both transistors by overlapping them, but you must look what (overlapping source or drain) will give you most optimize layout. I think overlapping drain of PMOS will reduce the parasitic more compared to overlapping source.
@@MicroelectronicsVLSIDesign Thank you for your reply. I did overlap and design but while i m doing drc it shows metal layer must have .233um spacing in 180nm scl. i will overlap drain and check parasitic cap.
@@sunilrathore3447 may be that error is because of not a proper overlap or you have placed two metal lines closely at some other place in your layout. You can check at which place that error is present by highlighting the error in layout window.
I didn't find this library
How can I get it
Can you point out from where i can download SCL 180 pdk
?
Its not a free PDK, you can get it only from SCL INDIA
what is "Pcell evaluation failed" i am facing this problem in scl 180 nm pdk while placing a capacitor "cmim_sq" during layout
community.cadence.com/cadence_technology_forums/f/custom-ic-design/41911/pcell-evaluation-failed-issue
Dear sir i m waiting for second part of this video when You upload second part of this video
You Can tell me what are you looking for I will try to upload that part.
steps for LVS, DRC and postlayout simulation for this library (SCL 180nm)
Sir..my pre layout and post layout is mismatch. I tried inverter aslo.but pre layout & post layout mismatch. I am using SCL PDK. I don't know why it is coming like that
By pre layout and post layout do you mean Schematic and Layout?
can i overlapp both source of pmos while designing 2 input nand gate and connect to vdd? will it work or give some error?
Yes you can have one source for both transistors by overlapping them, but you must look what (overlapping source or drain) will give you most optimize layout.
I think overlapping drain of PMOS will reduce the parasitic more compared to overlapping source.
@@MicroelectronicsVLSIDesign Thank you for your reply. I did overlap and design but while i m doing drc it shows metal layer must have .233um spacing in 180nm scl. i will overlap drain and check parasitic cap.
@@sunilrathore3447 may be that error is because of not a proper overlap or you have placed two metal lines closely at some other place in your layout. You can check at which place that error is present by highlighting the error in layout window.
@@MicroelectronicsVLSIDesign yes got it..thabkyou
how to install cadence on windows
I don't think you can install Cadence in windows. If you have one then installation manual will also be there in some folder.