Designing 7-nm IP, Bring It On Moore! | Synopsys

In keeping with Moore’s Law, discover how Synopsys is developing 10nm/7nm IP for SoC designs. Learn how tradeoffs are made in electrostatics, leakage, pattern, manufacturability and transistor performance to meet PPA requirements. See how quantum effects impact FinFET designs in terms of fin width, fin height and anything that impacts bandgap. Technology can be scaled to 7nm, bringing performance and power improvements.

[@jerrywatson1958]

I find it amazing how the design tools can account for variations and other potential defects before printing to silicon. Between packaging innovations, 3d, and multi-layer designs, when will Moore's law end? At the atom level with graphene? I can see those MP being replaced with graphene in the near future. Great talk, thank you.

[@YashN009]

It was amazing and very much informative. I learned many things.

[@bestelectronicmusicfromnew5189]

that was a very interesting clear talk. my zx81 had 1kb memory with a 15kb addon cartridge. can the tape deck still jog and disrupt hdd-memory read process for 7nm?

[@saisatish1743]

Nice

[@florin604]

Intelligence that makes one humble.

[@bobhumplick4213]

must have been at a dinner. all i can hear is forks and glasses clanking. distracting to me. if not a dinner then somehting is clanking