Writing Basic Testbench Code in Verilog HDL | ModelSim Tutorial | Verilog Tutorial

[@brupts7297]

Starts off in english then suddenly goes indian....perfect...Can we PLEASE add to our title "*Tutorial Name* + *THE LANGUAGE YOU'LL BE USING*"

[@neelshejwalkar5153]

Lmaooo

[@lemone9639]

Wouldn't make a difference, you think Indian is a language

[@daniyalbaig2092]

very good easy to understand no bulsh@t very appreciated

[@fatjellyfish9478]

was very helpful, thank you very much.

[@nomanmasud4807]

Amazing, outstanding, able to understand, extraordinary experience .
Thanks Sir sumair Aziz.

[@ElectroDeCODE]

Thanks

[@spaceghost8327]

this looks like it would be an amazing video to share with classmates but the audio quality is horrendous

[@LaithKhoury]

What do you mean easy to understand? Is this even in english? Horrible quality but I have to do what I have to do to complete my hw.

[@nidatasneem1792]

excellent

[@ElectroDeCODE]

Many thanks

[@MatheusReatoBellandaPiao]

Can we please not use English titles for videos that aren't in English? It's very frustrating to get into the video hoping to find the solution to a problem and boom, can't understand a word.

[@tls2257]

The slides are good but can't understand a word you say.
Consider adding captions for future videos, thanks.

[@ElectroDeCODE]

Thanks for your valuable suggestion dear.

[@JuanMartinez-v3e]

took me 6 minutes to figure out he wasnt speaking english

[@_SureShots]

Don't take it otherwise. But, are you from Pakistan?

[@chass7050]

Buy a good mic lil bro

[@ElectroDeCODE]

Noted. THanks