Test Bench writing in Verilog | #16 | Verilog in English | VLSI POINT

[@hbtech501]

In a single day, I watched all the videos from this playlist. Very useful content. Thank you, ma'am.

[@ukmssu]

Thank you for this amazing Verilog tutorial playlist! It helped me clear my basics and understand Verilog better. Grateful for your clear explanations and valuable content! 🙏🙂

[@danielmsheliza220]

Thank you so much, great series! this helped so much as one of the most extensive verilog learning experiences on youtube!

[@lofi_song562]

Tomorrow in our campus interview is there for 5Lpa
I just see your video 😊thxx

[@gxdx697]

thank you for your verilog tutorial! helped me alot in my HDL course..

[@Cookwithdivya12]

Is this entire playlist.. Or there some topics need to be covered

[@unique8831]

Please continue this series madam

[@VinaykumarSingh-j6r]

Thank you mam your explanation is very good.

[@jeeveshvanga2598]

Thanks a lot mam .so usefull these whole series.🙏🙏

[@chandumadhumanthi]

Thank you Very much for the wonderful tutorial its very fruitful.

[@harinebala8454]

Is the entire playlist of vlsi is over or some more videos are yet to be uploaded mam?

[@ganeshbagnal6524]

In this which type of delay is mentioned? Is it Regular Delay or Intra-Delay ??

[@beasthitesh902]

which software should i use to code in verilog??
ma'am please answer

[@vlsipoint]

Modelsim, Xilinx Vivado or EDA playground

[@beasthitesh902]

@@vlsipoint thank you

[@ganeshbagnal6524]

In earlier videos explained that Initial Statements are executed Parallel. In Full Adder Test Bench-1, all the initial statements executes parallel then, a,b, cin values will be always 0 as per first initial statement. Is my understanding correct?

[@Prabh_cc]

Traveler you complete one more tutorial 🥳

[@md.jannatulnayem4328]

Put more content in this chanel Sweta

[@mrtechindia]

Ma'am if u have any test bench waveform which is quite helpful to get more about on that

[@gvenkatesh6671]

Hi Madam, when you will be start SV and UVM

[@ΝικΝοκ]

hi , nice series ! helped me alot to understand !

[@susheelapatgar3640]

Thank you so much mam. ♥️I reffered your notes for my placement preparation.And I love ur voice 😁.i didn't comment any of ur vdo, its just because i downloaded the videos.❤️🙏 ..{•_•}..

[@harshalzaveri7995]

Why you didn't assign value to reset in up_down counter's test bench code?

[@kingwon7995]

Hello Ma'am!!
Please can you make a series on VHDL Language too!!

[@shrutichavanaik5782]

Thank you mam 😊❤

[@UswaImtiaz-rz4si]

as a beginner, i can't understand a thing you taught. It would be appreciated if you go more in depth.

[@sentient1640]

I think you have made an error in the JK flip flop test bench code. The values of J K are always changing at falling clock pulse.

[@shrishu_gupta]

Thanks a lot mam ..

[@keeplearning9079]

Hi mam.
The invite link was expired.
Could you please update with new working link please.

[@nikitagalar5638]

Ma'am ...How to increase more knowledge.