It is in fact not the gate voltage but the gate-source voltage. In 90nm, your supply is perhaps 1.2v, In the inverter case, the pmos source is connected to the supply. If gate is also connected to the supply, then you don't attract any holes to form the channel because Vgs=0. Start lowering gate towards 0V. When gate goes about 0.35V below source (Vg=0.85V), or gate is negative with respect to source or Vgs=-0.35V then you have certain amount of holes already attracted under the gate and the transistor is just about to start conducting. If you lower gate voltage even further, the channel becomes "fatter" and the transistor conducts stronger. If the drain of the pmos is connected to the drain of an nmos which is turning off at the same time like in the inverter, then the stronger you turn on the pmos, the weaker the nmos becomes - in other words pmos wants to conduct current but nmos opposes it. When nmos is off, the pmo current cannot flow anymore and the only possibility is for the drain of the pmos to become equal to the pmos source voltage, because current is 0 for Vds=0. If you're doing circuits, I recommend that you learn device physics well, but then keep it at the back of your mind while you only use the concepts of current, voltage and charge to analyse the circuit operation. If for every circuit you start thinking in terms of holes and electrons, things become very complicated and this is not an useful approach.
Sir, u r really doing good videos. Thank you very much. I have one doubt on this. Please tell how did u get 2x drain n 1x source. If u split a transistor, u should get 2x drain n 2x source.
Hi, your lectures are so good. Many people will get benefit from these lectures. I have one question that, in LOD topic why you are considering 2 drains at a time. If we will see cross sectional view OD continuation will not be there under poly. And 2nd till i thought LOD effect is due to stress around it's edges. due to that OD may shrink or extend little bit. to insert dummy we can avoid this problem.
Thank you for ur excellent lecturing sir am learning a lot from u. And in this LOD concept still i am not clarified with that change in Vth i.e increase and decrease of Vth,and also hou is drain area is increasing? could u please explain it clearly in next vedios..If possible....
Thanks for the explanation.. I have few doubts.. 1. about vt change in pmos and nmos.. why it is different for these two types, means for pmos vt is decreasing and for nmos it is increasing right? 2. when you say that charge carriers are increasing in pmos/nmos are you referring to ions in substrate/well or diffusions(S/D)? please help me understand this. Thank you..
pmos having a local sub (Nwell) , but Nmos is connected global sub (Psub), cos of this we have high chances of LOD with Pmos devices compared to nmos , but it doesn't mean nmos doesn't have any LOD, nmos also will affected by LOD, and also mobility carriers of Pmos is slower then Nmos , cos of this pmos will switching speed will became slow , all those reason is important
Hi sir am not understanding while doing fingering how drain area is doubled comapred to source area could you please clarify this one. Please upload STI effect video also . I am learning so many things from your lectures Thank you so much ..
Sir u explained dd sharing is good. Because drain is collecting the current. I agree that. What about in MMOs the source is collecting the current. So ss sharing is good in nmos?
actually this good concept , in my layout i used to connect output terminal for sharing and merging , for pmos dd , and nmos ss , but its also depend on the circuit , its a not like every time il do like this ....
The videos your uploading is helping me a lot...can u please upload the videos about basic interview questions about layout enngr and also ESD TOPIC and sir tell me in BGR why we use bjts instead of fet ..I failed to answer this question in my interview
In BGR, BJTs are primarily used ; but there are architectures where a FET is also used. Whether its a BJT or a FET, the diode voltage drop across it is utilised for PTAT and CTAT cancellation so as to get a ZTAT voltage. In a BJT, the VBE is directly proportional to temperature (go through IC-VBE equation of BJT) ; hence it is easier to cancel whereas in a FET, the VGS is not directly proportional to temperature (refer ID-VDS equation of FET) . Hence BJTs are preferred over FETs. However in the BGR architectures which use FET for diode voltage drop, there the FET need to be biased in subthreshold region so that VGS across it is directly proportional to temperature.
@@pragyansundarbiswal6663 absolutely correct explanation. Just wanted to add further that while using BJT, the current across the diode (BJT) -- whether assumed constant, or a PTAT -- does not affect the performance of the BGR performance. BJTs offer an attractive method to overcome PVT variations by simply adding them in parallel.
Thanku sir ... For sharing knowledge .. it's too helpful. Bcoj of your vedio i got intrest in analog layout and many concept become clear Again tqsm..👍
Sir i have doubt,Plsss give me reply.... In this video (please check time at 13:24) you explained that..In P-mos majority carriers are holes.... My doubt is.... You showing the N-WELL and you telling like holes are majarity carriers in N-WELL. I think electrons are the majarity carrier's in n -well. Pls clear my doubt 🙏🙏🙏🙏🙏
This LOD effect can also be called STI effect. So, whenever there is a diffusion break STI will be there which puts stress on our active devices and changes their Vt. According to me to reduce this effect we can merge the active devices and put some dummies at the edges so that STI won't effect the devices at the edges and the devices in the center experience no STI/LOD effect as there is no diffusion break. Am I wrong here? If yes, plz help me to get this concept?
hello sir, how that drain area is increases in b/w drains we have one poly wright. i think there is no connection b/w the drains. how can we take it as a single drain?
Ur splitting drain and source , areas by adding numbers of fingers and multipliers , right ? We never use single finger & multiplier devices most of the place's , so this effect is happening
@@analoglayoutagain we are increasing the carriers right then current will increase then (when we add dummy or enclouser increases)how dummies will take care LOD?
It is in fact not the gate voltage but the gate-source voltage. In 90nm, your supply is perhaps 1.2v, In the inverter case, the pmos source is connected to the supply. If gate is also connected to the supply, then you don't attract any holes to form the channel because Vgs=0. Start lowering gate towards 0V. When gate goes about 0.35V below source (Vg=0.85V), or gate is negative with respect to source or Vgs=-0.35V then you have certain amount of holes already attracted under the gate and the transistor is just about to start conducting. If you lower gate voltage even further, the channel becomes "fatter" and the transistor conducts stronger. If the drain of the pmos is connected to the drain of an nmos which is turning off at the same time like in the inverter, then the stronger you turn on the pmos, the weaker the nmos becomes - in other words pmos wants to conduct current but nmos opposes it. When nmos is off, the pmo current cannot flow anymore and the only possibility is for the drain of the pmos to become equal to the pmos source voltage, because current is 0 for Vds=0.
If you're doing circuits, I recommend that you learn device physics well, but then keep it at the back of your mind while you only use the concepts of current, voltage and charge to analyse the circuit operation. If for every circuit you start thinking in terms of holes and electrons, things become very complicated and this is not an useful approach.
Sir, u r really doing good videos. Thank you very much. I have one doubt on this. Please tell how did u get 2x drain n 1x source. If u split a transistor, u should get 2x drain n 2x source.
Hi, your lectures are so good. Many people will get benefit from these lectures. I have one question that, in LOD topic why you are considering 2 drains at a time. If we will see cross sectional view OD continuation will not be there under poly. And 2nd till i thought LOD effect is due to stress around it's edges. due to that OD may shrink or extend little bit. to insert dummy we can avoid this problem.
Thank you for ur excellent lecturing sir am learning a lot from u.
And in this LOD concept still i am not clarified with that change in Vth i.e increase and decrease of Vth,and also hou is drain area is increasing? could u please explain it clearly in next vedios..If possible....
Thanks for the explanation.. I have few doubts..
1. about vt change in pmos and nmos.. why it is different for these two types, means for pmos vt is decreasing and for nmos it is increasing right?
2. when you say that charge carriers are increasing in pmos/nmos are you referring to ions in substrate/well or diffusions(S/D)?
please help me understand this. Thank you..
Thank you for the video sir. While doing layout, we usually fix LOD only for PMOS (by adding a dummy device). Why is it not fixed for NMOS?
pmos having a local sub (Nwell) , but Nmos is connected global sub (Psub), cos of this we have high chances of LOD with Pmos devices compared to nmos , but it doesn't mean nmos doesn't have any LOD, nmos also will affected by LOD, and also mobility carriers of Pmos is slower then Nmos , cos of this pmos will switching speed will became slow , all those reason is important
@@analoglayout Thank you for the explanation sir.
@@bhavanavalaboju6098 Hope you understood
@@analoglayout Yes sir. I understood it now.
How drain area is more than source? And why we have double drains can u explain briefly?
Hi sir am not understanding while doing fingering how drain area is doubled comapred to source area could you please clarify this one. Please upload STI effect video also . I am learning so many things from your lectures
Thank you so much ..
i'l try to upload one tool based video for this , so that u can understood , very easy ..... this week end , keep support our channel
I have the same question
Sir u explained dd sharing is good. Because drain is collecting the current. I agree that. What about in MMOs the source is collecting the current. So ss sharing is good in nmos?
actually this good concept , in my layout i used to connect output terminal for sharing and merging , for pmos dd , and nmos ss , but its also depend on the circuit , its a not like every time il do like this ....
@@analoglayout ok sir thanks...;)
How do we consider the drain of g1 in the source of the g2
The videos your uploading is helping me a lot...can u please upload the videos about basic interview questions about layout enngr and also ESD TOPIC and sir tell me in BGR why we use bjts instead of fet ..I failed to answer this question in my interview
chk this link : drive.google.com/drive/folders/1-Aj_1n_SS-U8k29WHqhYUOKeFqe8va2m?usp=sharing
Actually it is a pn diode its not bjt because of connections we unintentionally a bjt is formed that's why we are using bits
In BGR, BJTs are primarily used ; but there are architectures where a FET is also used. Whether its a BJT or a FET, the diode voltage drop across it is utilised for PTAT and CTAT cancellation so as to get a ZTAT voltage. In a BJT, the VBE is directly proportional to temperature (go through IC-VBE equation of BJT) ; hence it is easier to cancel whereas in a FET, the VGS is not directly proportional to temperature (refer ID-VDS equation of FET) . Hence BJTs are preferred over FETs. However in the BGR architectures which use FET for diode voltage drop, there the FET need to be biased in subthreshold region so that VGS across it is directly proportional to temperature.
@@pragyansundarbiswal6663 absolutely correct explanation. Just wanted to add further that while using BJT, the current across the diode (BJT) -- whether assumed constant, or a PTAT -- does not affect the performance of the BGR performance.
BJTs offer an attractive method to overcome PVT variations by simply adding them in parallel.
Keep uploading new vedios 💫✨️
sir can you explain about shallow trench isolation also please sir
Thanku sir ... For sharing knowledge .. it's too helpful. Bcoj of your vedio i got intrest in analog layout and many concept become clear
Again tqsm..👍
How a single transistor have two drains, two fingers means 2 sources & 2 drains will present either s or d will be shared then how LOD occurs
Better read it properly , 2 finger device have 1 source , 2 drain or 2 drain 1 source , so in this case one us bigger then other ? So Lod happen
Hello Sir, videos are well articulated.
Also request to add video on Poly space effect.
sure , il do
Thanks for the quick reply sir. Awaiting for it😊
Sir i have doubt,Plsss give me reply....
In this video (please check time at 13:24) you explained that..In P-mos majority carriers are holes....
My doubt is.... You showing the N-WELL and you telling like holes are majarity carriers in N-WELL.
I think electrons are the majarity carrier's in n -well.
Pls clear my doubt 🙏🙏🙏🙏🙏
Some time i may be wrong , refer the text book
@@analoglayout I think this time you are absolutely wrong not may be. You need to modify this video
@@md.arifulislam7793 refer me the correct content - i will read & modify my mistake - much appreciated for this review
This LOD effect can also be called STI effect. So, whenever there is a diffusion break STI will be there which puts stress on our active devices and changes their Vt.
According to me to reduce this effect we can merge the active devices and put some dummies at the edges so that STI won't effect the devices at the edges and the devices in the center experience no STI/LOD effect as there is no diffusion break.
Am I wrong here? If yes, plz help me to get this concept?
Exactly correct
@@analoglayout Thanks for replying,
So, I can say that Multipliers face more LOD effect than fingers. Correct?
If this is the case ..the OD break will occurred in middle ,how to prevent LOD effect (meanthat what are the techniques)..
How come you have 2 drains together can you explain. While doing the fingering, we can SDS or DSD.
Sds has 2 source area , dsd has 2 drain area
is the STI available in all PDK?
Ys, it's default process of the foundry, doesn't required any masking layer in addition
So, in every Mos of all PDK has this STI thing & therefore LOD happens in all PDK. Right? Thanks for you replay.
How the area of source and drain get changed if u go for sharing of drain and how mobility varies?
exactly, the same question i have.
hello sir,
how that drain area is increases in b/w drains we have one poly wright.
i think there is no connection b/w the drains. how can we take it as a single drain?
Ur splitting drain and source , areas by adding numbers of fingers and multipliers , right ? We never use single finger & multiplier devices most of the place's , so this effect is happening
Sorry I think the LOD effect is actually based on the distance of active regions from STI ..... i found this video quiet confusing...
Both are correct , don't confuse your self , you can explain with respect to sti stress also
LOD is one of the cause of STI right ?
Both are different , but one can affect another one , problem wil be more then
Thanks alot for clarification of LOD. Hats Off.
Your welcome
how drain area is 2x , cannot understand the diagram , if we have two fingers than we have source area 2x and drain area x
i know most of them is understand this concept , i'l upload a cadence virtuoso based video , so that u can understand this very easy ....
Sir how to overcome by LDO problems
1.adding dummy , 2.increasing well size or keep far away our active devices from the well boundary
@@analoglayoutagain we are increasing the carriers right then current will increase then (when we add dummy or enclouser increases)how dummies will take care LOD?
how to avoid LOD effect using fingers concept only
gng to multiplier , adding dummy
u mean we cannot avoid in the circuit which is followed by FINGERING concept
one more thing when to go wit FINGERING and when with MULTIPLIER
finger have some max limitation , based on that schematic engg will design the circuit , so its not a work of layout engg
pls watch , finger & multiplier video in our channel
Sorry , I found it bit confusing