CROSSTALK & SHIELDING - English Version
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- เผยแพร่เมื่อ 20 ก.ย. 2024
- This video contain CROSS-TALK & SHIELDING in English, for basic Electronics & VLSI engineers.as per my knowledge i shared the details in English.
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sir kindly post a video for signal integrity sir your videos are very awesome to understand
This is really good. I am in Analog design but continuosly watch your videos for knowledge and better understanding.
Welcome
I am a daily costumer to your channel good work brother keep it up
Thank you for the video. A few questions:
1. Assuming an all-digital IC, there are two obvious power nets: VDD and GND. You suggest the shielding network to be connected to another ground net called VSS. Is the VSS connected to GND somewhere on the IC or outside the chip?
2. Can shielding be also done with nets connected to the supply network, VDD?
3. Are all clock networks in ICs routed with shielding?
Thanks!
The way of explanation is awesome,one small doubt sir is there we have different types of cross talks or the types are related regarding metal to metal and metal to subtrate as you explained in video.types of crosstalk is related to this or any else are there?
I'm not able to understand your question
Can you please explain types of crosstalk
hi sir,, in this video you told that you will tell( 1.05 sec) about critical net and sensitive nets .....but u did not covered that ..so please make a note sir...and thank u once again such a great knowledge sharing
Nice explained sir
Keep...It up.
Superb CLS and it is very useful thank u
Welcome 😊
one doubt , Should we follow some generalized thing to maintain width and spacing for shield or minimun is fine , as this will also put some cap over the signal ?
ya , we have to keep mim width , how ever its gng to connect to gnd , so no need to worry abt cap , only side wall and fringe cap is main prob , by connecting a gnd , this problem also we can solve
Hi, Why Generally shielding lines are connected to VSS not to VDD ?
Sir I have a small doubt in cross talk prevention for suppose distance r width of the two metal will increase according to formula of the capacitance. While is increasing distance between two metals capacitance increase and also electric field increase then more unwanted siganls also created..?
Distances increase , cap will decrease
bro the formulae of cap is c = epsilon*A/d
for which nets we have to follow side wall shielding.....i mean names of the nets..
net is important , we have some criteria based on that we have to do shielding , most of the time side wall shielding they prefer
@@analoglayout why not other?
Nicely elaborated.
Why should connect shield line connect vss or gnd why should not connect vdd
Sir I want to know what is Critical nets and sensitive nets please make a comment sir
this details u will get from schematic engg , but basically bias block , clk signal , etc ...
In co axial shielding why we use top metal on upper side and low metal in bottom side
Then , how will u form a co-axial shielding ?
If you need to protect the net from all sides means you have do it from 4 sides right! So for top & bottom you are using higher & lower metals. For side wall we are same metals
sir,
thank for video
can i get some more documents related to signal integrity or please provide site details for signal integrity .
Sir please make a video on chemical mechanical planarization(CMP)
Why high frequency signal discharge to body
in side wall shielding why should not go for higher metal is there any problem sir
in this you were explaining with m1
what metal ur using for routing , same metal only u have to do shielding ... if m1 ur routing same m1 should be used for shield , if m2 , m2 u have to use
Hi.. bro
Your explanation is good..
I have small doubts regarding shielding
1. Why we mostly connected shielding nets to ground? Why not to Vdd? In which cases shielding nets connected to Vdd?
2.what happens when we do half of the shielded net connected to Vdd and half shielding of the net connected to the Gnd.? Both on the same net this is my IBM Client interview qns
3. Generally we avoid shielding to the high frequency signals? If do what happened.. for this qns I think delay of the net increase.. I expect from you.. another any reason?
4. Vref ,Vbais ,Vclk for which net you give high priority to do shielding and why?
1. based on the signal , we have to connect it to vdd or vss or gnd , but most of the time we will connect to gnd , bcos its a low impedance path compare to vdd,vss
2. how will u do half vdd, half vss ? its a useless methos , bcos any one half only will shield effectively , another half will get disturbance
3. high fq signal carry , high current & Fq , so u should shield high fq net
@@analoglayoutok tq bro
High frequency signal is nothing but clock signal,If you shield clock signal you will add more loading to it which will delay the signal,So we should only shield the place where we are seeing the cross talk,In general to avoid any disturbance fist we should plan to route these critical signals(usually in medium metal).so clock signals should not be shielded in general!
Vref is ref signal which is very critical in most cases we will do co axial shielding
bias signal can be done in sidewall again it depends on designer,some times he does not want any noice on it then go for co axial
vclk we will only shield where ever it is required!
Hi bro ,I want your contact no
Hi sir
Can you explain me virtuoso l and xl difference..
For sidewall shielding can we go for higher metal than a signal line?
No , same metal u have to use
@@analoglayoutCan I know the reason behind using the same metal for sidewall? Why not higher or lower metals than the signal line?
@@manishasutar8701 May be both will fabricate on same step if we use same metal for side wall. If we use higher r lower metal it will act like top & bottom shielding. I too don't know exactly but i thought in this way
Sir if we increase in width that more gap drc errors will come
There should be available space to avoid drc
Hi,clk signals and data signal in which signal we need to shielding? why?
Based on which is critical, or else shield data
Sometime we do shielding with VCC also ?
Ys , some time
bro nice
Good explanation!
thqqqqqq
Whether we have a parasitic capacitance between nwell & p-sub
Can u make a video on parasitic components.
ya , we have 4 cap , 4 diode , 4 resister , in one mos , gate to body , gate to source , gate to drain , drain to source , nwell to p sub , also
yap , sure ... soon
Thanks sir!
Is metal orientation is solution for cross talk between metals?
I thg , I've explained everything in this video , watch it Fully
How to interconnect two metals?
Using via
Sir I want STI video please do u upload sir?
ya ... will be uploaded soon
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