CMOS FABRICATION - English Version

This video contain CMOS FABRICATION in English, for basic Electronics & VLSI engineers.as per my knowledge i shared the details in English.
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[@shrikantkumar1102]

hi sir , when you are explaining p - diffusion so you have connected drain to n+ tap why ? should be connect source to connect N+ tap right ?

[@hasanimroze6089]

Excellent videos sir
Superb explanation

[@analoglayout]

thx for your comments

[@user-ep4hz6nq5y]

Sir ,is P substrate preferred than P+ and P-
??
I mean for substrate, medium p doping is preferred or which is preferred and why ?

[@riddhisehgal1766]

Amazing explaination sir 👍👍👍

[@analoglayout]

Thx

[@MBm107]

Hi sir I have doubt why pmos has N-Tap ??

[@analoglayout]

Refer the basics of CMOS cross-section view

[@kandrashilpasree114]

Sir why pmos bulk is connected to vdd and nmos bulk is connected to vss we want detailed explanation.if reverse means what happened???

[@mohammedafzal534]

To make the diode reverse bias otherwise if we connect the pmos bulk to vss it will be in forward bias then instead of flowing the current through the channel the current will flow along the substrate which we can say as a leakage current

[@kandrashilpasree114]

OK thank you sooo much

[@baloo212]

Sir in 12:39 you mentioned compulsory drain is connected to the tap for pmos and source connected to tap in nmos. What is the reason

[@analoglayout]

It's a act as a body connection , without body connection mosfet will not work , some theory says without body connection also mos will work but when you add bulk connection or body connection it will give one more reverse bias diode to prevent the leakage current.

[@baloo212]

@@analoglayout
Thank you for the reply sir. But why is specifically drain connected to tap for pmos and why is source connected to tap in nmos

[@analoglayout]

@@baloo212 source and drain are interchangeable , so u can make any terminal as a s or d

[@kennethpajatin4402]

very informative goodjob 💪💪

[@analoglayout]

Glad you think so!

[@prasadnakanaboina8701]

Sir can you please make videos on FINFETS

[@souravmukherjee4987]

Is there any video where we can learn it looking the process in lab?

[@satyasai7141]

Sir y we have to take only p substrate as the base y not n substrate has a base?

[@analoglayout]

its n well process , so they to p as a sub , for p well process , n will the substrate

[@satyasai7141]

@@analoglayout sir in layout the main substrate globally its i p substrate in cadance or synopsis y cant be it n substrate? In layout designing.

[@analoglayout]

n well process is having lot of advantage over others , so they r following this p sub for global

[@youthcentral493]

CMOS fabrication Tamil version please sir

[@iftikhar.1]

hindi version???

[@analoglayout]

sorry , i dont know Hindi . . . . ! ! !

[@studysourcechannelssc8603]

sir in step 4 you are removing photo resist and again y you are removing in step 5

[@niteshagrawal516]

Make video on finfet fabrication and its structure.

[@analoglayout]

sorry , i dont have finfit experience , i dont know

[@hemantpise3414]

Why ion implantation done by tilting 7 degree n why not verticalyyy

[@analoglayout]

To aviod channeling effect

[@KrishnaRaj-wv5zt]

Please tell me FINFET

[@vakeelmohammadansari8525]

PLS UPLOAD VIDEO FOR CLOCK GATING...

[@Dayasagar574]

Sir please uplosd ppt also in the description.

[@gadiboinarekha7193]

Hi sir thank you for your videos,I need information about MOSFET how it will work as a switch and Amplifier can you give explanation sir & Operation in 3 regions ,thanks in advance

[@analoglayout]

il try by this week end

[@gadiboinarekha7193]

@@analoglayout ok thank you sir

[@kalpanachowdary5308]

Can you please tell how wafer will creat sir??

[@analoglayout]

wafer creation is unique fab tech , i'l make a video for this

[@kalpanachowdary5308]

@@analoglayout thank you sir

[@ravaligangula7589]

Current gurinchi chapa andi in saturation region

[@analoglayout]

ravali , too basic i cant explain , spend some time in books , try to cover all the basic ,

[@abhinaygali5050]

Very 👌

[@youthcentral493]

tamil version vanum sir

[@analoglayout]

il do it asap ....

[@ravaligangula7589]

Epitaxial means

[@analoglayout]

that is one kind of metal , but so expensive then bulk wafer , so Epi wafer we are using

[@kirankumargongada4457]

Y we take p sub mostly y not n sub

[@analoglayout]

You can go for n sub also ...but due to ground connectivity in p sub we going to this

[@youthcentral493]

sir i pay amount

[@analoglayout]

hello brother , i've work at weekdays , so i'm sorry , when ever im free il make video then il upload , immediately i cant , and i created this channel to teach to others ,not to earn , bcos i love to teach , i'm not expecting any profit out of this , thx for ur comment .......

[@analoglayout]

Tamil Version , as per your request - th-cam.com/video/JVJMNZYvNhU/w-d-xo.html

[@ravaligangula7589]

Hmm sir

[@youthcentral493]

plz sir

[@analoglayout]

i'll do it bro , dont worry

[@youthcentral493]

bro