Your VLSI Related videos are very interesting and in a very understandable way. Thank you. "Pls could you make a continuation of this videos like Case 3 & Case 4". 🙃
Thanks you for sharing these information. I have gone through few articles and found that Hold time check depends on clock frequency if there is 1. half cycle path 2. where we have to do hold time analysis at previous/next clock edge. waiting for more contents in this series of STA.
Half cycle is one type of exception, so for hold analysis we r getting an extra half cycle margin,this effectively adds a half-cycle margin for hold checking and thus results in a large positive slack on hold..
sir your tutorials are amazing , could you post a video of real time projects in physical design using icc2 tool from the netlist to placing macros to tapeout
There is no such constraints for half cycle path. As the launch and capture edge are differently triggered so tool will automatically calculate slacks as per edges. Please correct me if i am wrong.!! @Team VLSI
Hold is not depend on clock period If we increase combo delay or decrease combo delay it will occur but set up is depend upon clock period if we change frequency set up will occur nor before either after changing frequency Setup is depend on clock period
Hi Anand, Kindly go to 19:00 onwards in video and think, In case of half-cycle path, there is hold violation and we increase the clock preiod (decrease frequency), Is there any chance to meet the hold timing???
Hi Aravind, There are lots of tutorial availabel on general TCL and PERL. But Yes I will make some tutorial specifically for VLSI people. It might take some time but will do.
just I have a dout, If we don't need to specify in sdc then why we have clock exceptions such as half cycle ,multi cycle and false paths in sdc. SDC will contain all information regarding this right?
Your tutorials are very detailed. Thank you and keep making them. It really helps
Thanks a lot shubham for your appreciation , We will try to provide our best.
Your VLSI Related videos are very interesting and in a very understandable way. Thank you.
"Pls could you make a continuation of this videos like Case 3 & Case 4". 🙃
Thanks you for sharing these information.
I have gone through few articles and found that Hold time check depends on clock frequency if there is 1. half cycle path 2. where we have to do hold time analysis at previous/next clock edge.
waiting for more contents in this series of STA.
Right Manish,
We will add soon.
Please post the video dealing with latch and flip flop combination.
Hi, thanks for sharing. Does it mean, we can decrease clock frequency and gain the margin of setuptime & holdtime?
Half cycle is one type of exception, so for hold analysis we r getting an extra half cycle margin,this effectively adds a half-cycle margin for hold checking and thus results in a large positive slack on hold..
Right, Devarun.
sir your tutorials are amazing , could you post a video of real time projects in physical design using icc2 tool from the netlist to placing macros to tapeout
Okay. We will try.
Thanks for this opposite edge example
You Welcome Rutwik.
Share the video maximum in your groups!!!
@@TeamVLSI yes sir.
great explanation indetail...
Glad it helped Venkata!
There is no such constraints for half cycle path. As the launch and capture edge are differently triggered so tool will automatically calculate slacks as per edges.
Please correct me if i am wrong.!! @Team VLSI
Right Rishikesh.
No need to specify half cycle path in SDC by construction they will be inverter in the clock path
Is this correct..?
No need to specify. It will be checked based on leading or trailing edge triggering.
Can u please let me know the video for timing equation for flip and latch
It will be published soon.
@@TeamVLSI Bumping up interest for ff-latch paths. It was promised a year ago ;-)
Hold is not depend on clock period
If we increase combo delay or decrease combo delay it will occur but set up is depend upon clock period if we change frequency set up will occur nor before either after changing frequency
Setup is depend on clock period
Hi Anand,
Kindly go to 19:00 onwards in video and think, In case of half-cycle path, there is hold violation and we increase the clock preiod (decrease frequency), Is there any chance to meet the hold timing???
Why uncertainty is high in half cycle paths
No it's not.
No clarity.. picture is buffer😫
Sir, make videos on tcl scripting and perl scripts
Hi Aravind,
There are lots of tutorial availabel on general TCL and PERL. But Yes I will make some tutorial specifically for VLSI people. It might take some time but will do.
sir, what about CPPR why we are using CPPR for hold time ?
Sir i have a doubt why there is opposite edge for setup check and hold check??
Can't we do the same on the same setup edge?
Hi Abhishek,
Sorry, I didnt get you point. Can you reframe your question pls?
FF2 is a negative edge flioflop
No need to specify half cycle path in sdc, tool will report automatically based on rising edge and falling edge
Rightly said!!! I was looking for this response.
just I have a dout, If we don't need to specify in sdc then why we have clock exceptions such as half cycle ,multi cycle and false paths in sdc. SDC will contain all information regarding this right?
I have a dout sir. Whether ZERO cycle paths are exist?
We define multicycle and false path only in sdc.
@@TeamVLSI thank you sir