Positive edge detector circuit and rising edge detector

[@psujith9300]

Thank you sir. Very clear explanation

[@VLSI-learnings]

Thank you

[@anilkumar-zc5bk]

very good explanation thanks!

[@VLSI-learnings]

Thanks

[@sai3754]

sir,if we have o/p should be be high for half clk pulses .Then how to do that

[@VLSI-learnings]

You have to use neg edge flop

[@sai3754]

Sir, how can I contact you
I have doubt regarding that postive edge and negative edge sir

[@saketkumar9852]

Sir , please come with these types of questions

[@VLSI-learnings]

Ok

[@smsrivastava100]

Sir is there any delay in o/p of flip flop as it is coming after another clock edge? Or this is not an idial flip flop

[@VLSI-learnings]

if you write serial flop code and give the data as 0 to 1 then output 0 to 1 it take two clocks . if we flop any signal it will come at next clock

[@2K22VLS16SHIVSHANKERYADAV]

excellent

[@VLSI-learnings]

Thank you