maximum operating frequency calculation of Sequential circuits

[@vaikh8450]

That's the quality content taught exceptionally well !!!

[@VLSI-learnings]

Thank you

[@ANKITSINGH-vb9hn]

Thanks boss....u explained very nicely and calmly

[@VLSI-learnings]

You are most welcome

[@pavanbhandari1177]

good explanation @DIGITAL SRI

[@VLSI-learnings]

thank you

[@SurajKumar-nz6qy]

In second case where total delay is(3+1+1) that is on the posedge of clock ,it will also not captured at second ff,right?

[@VLSI-learnings]

Can you please write the question again . i am unable to get your question

[@PranavSingh-ur9ic]

that last 1 is the setup time,it is not included in the delay ,it means data is taking 4 ns to change

[@omprakashpatel6322]

what is the max freq of the circuit if 10 is written under the cloud. nothing else is mentioned?

[@ravindratomar9916]

Plz upload video on previous gate solutions , of the hold/setup questions.

[@VLSI-learnings]

Ok

[@ashwingondane4105]

how to calculate max freq of operation when clock skew is present?

[@VLSI-learnings]

i did not explain clock skew concept here . As per RTL design point of view clock skew will be 0 (synthesis will run 0 clock skew and in STA run they will consider all skews )

[@ashwingondane4105]

@@VLSI-learnings Could you kindly make a video on it. It will be helpful. Thanks.

[@rojarohith8022]

Let's say there is a case where hold time is more than the propagation delay. Does all your formulae still valid??

[@VLSI-learnings]

There is hold violation then design will not work ...in this class I did not discussed any hold violation concepts here

[@srinivasv7511]

It is not lanched it was Launched Flipflop.

[@VLSI-learnings]

Ok

[@sudhakiran5799]

Sir please provide contact number

[@ahyungrocks5509]

Not able to follow with poor audio and images