I'm dealing with solder mask expansion issues on a BGA with a fabricator right now, and this really helped me understand what they are asking for. These detailed fab tutorials are SO helpful. Thank you!
Good video. At my work we set expansion to 2 mils and minimum sliver to 4 mils. When a minimum sliver violation is triggered (fine pitch components) we manually remove the solder maks in Altium. It is better to don't have the solder mask rather than having to scrape the PCB between pads removing incomplete solder mask.
I got some valuable information from your comment. My issue is Thanx for information. I am still not clear : what "MINIMUM" values should be used for SolderMaskExpension and MinimumSolderMask Sliver ? The real problem come , when one, use a Microcontroller with 100 pins. I am using ATMEGA2560 , pad size is 11.2mil (.28mm)... SolderMaskExpension default Value is 4mil. I am getting Design rule errors. Errors goes if I keep "MinimumSolderMask Sliver" VALUE to 0.8mil. Please let me know the real practical values in my case. Shall I reduce SolderMaskExpension Value to 2mil or 1 mil ? and Increase "MinimumSolderMask Sliver"
I really like their delivery of this kind of videos. Very casual discussion, not too formal and serious but freakin super informative and real world. Thanks man!
Another thing is to set the layer colours I think is very important, working on Altium for years, Red on the top layer gives a lot of eye strain. I use a very light/pale green colour which is easy on the eyes, people can try which ever they think is good for them. Hope this helps.
I appreciate the thermal example at 13:33. I know it isn't the point, but it did make things more clear for me, because the surrounding copper fill instead of a trace was a concrete reason to need it.
OMG first?! This is where knowing your fabricator's registration capabilities becomes paramount. Design within them and Bob's your auntie. For those of us who go to the rapid prototyping fabricators, this has to include choosing component footprints that won't challenge their capabilities. Another consideration is if you need to route traces under the solder mask slivers between pins.
Routing between pins under solder mask slivers was where this first came up for me. Doing a really dense board, some of the components are so close that you had these small slivers all over the place. Fab guys just said "over 5 mil slivers preferred" and that was their only guidance.
Thanx for information. I am still not clear : what "MINIMUM" values should be used for SolderMaskExpension and MinimumSolderMask Sliver ? The real problem come , when one, use a Microcontroller with 100 pins. I am using ATMEGA2560 , pad size is 11.2mil (.28mm)... SolderMaskExpension default Value is 4mil. I am getting Design rule errors. Errors goes if I keep "MinimumSolderMask Sliver" VALUE to 0.8mil. Please let me know the real practical values in my case. Shall I reduce SolderMaskExpension Value to 2mil or 1 mil ? and Increase "MinimumSolderMask Sliver"
The solder mask sliver value should take precedence, and the specific value that your fabrication house will guarantee is placed correctly will depend on their capabilities. Typically the minimum value is 5 mil, but some fabrication companies can do smaller than that. Solder mask expansion should be smaller than the default value, I usually use 1 mil so that this allows for a very small amount of misregistration when the stackup is being built. If you are using a BGA footprint with oversized pads, you can apply a negative mask expansion so that you have a solder mask defined pad.
Hi Zach - Altium reports minimum sliver violations but it doesn't report an error when the sliver is zero or less i.e. when components are located close together. This could lead to manufacturing problems if the solder bridges between pads. Is there a way to setup a design rule to detect when there is no mask clearance between pads of different surface-mount components?
As long as there is some solder mask sliver (greater than 0 mil thickness), then you will be able to see the solder mask sliver rule will violation if you run a rules check manually. It just might not show the cue visually in the same way it does with copper-to-copper violations. If you put two components so close together that the expansion totally removes the solder dam between the two components, then the dominant rule will now be the component clearance and not the solder mask sliver thickness. So let's say for example you set 2 mil minimum sliver with 3 mil expansion per pad by default, and let's say you set the pad-to-pad clearance to 10 mils. If you put two component pads near each other with 6 mil or smaller spacing, I've found you only trigger the clearance rule but not the sliver rule. Hopefully that makes sense; the solder mask sliver rule only triggers if there is some solder mask sliver that exists between two pads, so if you eliminate it with expansion then the only relevant rule is the clearance and not the solder mask sliver.
Nice video! We once had a problem with an electrolyte cap whose pad detached from the PCB (delamination?). I think the solution was to create a bigger pad and have a negative solder mask expansion so that the solder mask stops the pad from detaching. Is this a valid approach?
When did the delamination occur? Did this happen on an SMD cap during reflow or was this manually soldered? If it was manually soldered then your problem might be that the soldering tip is too hot. I've had this happen on small pads when hand soldering small components. If it's during reflow then that is pretty unusual, I've never seen that happen. You could use a bigger solder mask defined pad, but I'm not sure how much larger the pad needs to be to get greater adhesion, but it should scale linearly (double the pad area = doiuble the adhesion strength).
@@Zachariah-Peterson Thank you for the answer. I think it happened after reflow during transportation, the electrolyte capacitor was about 10mmX10mmX10mm big. In my opinion it is very unusual, especially if the board was only heated once for reflow and didn't go through any additional thermal cycling.
I understand why a manufacturer or fabricator might want to apply positive expansion to correct for likely errors in their process. I understand why the original designer would want to specify negative expansion, to mechanically hold the pad on. But why would the designer specify positive expansion, instead of just making the pad a little larger? Are thermal relief requirements that tight? Is the copper-copper clearance typically more than the minimal mask sliver size, and they're just trying to minimize the adjustments made later by the manufacturer?
In my opinion, just from a practical standpoint, it's a lot easier to change the expansion than it is to change all the pads in your footprints. If you're downloading your footprints, those pad sizes are already set, but you can really quickly change the mask expansion for all the components in the design rules. If it's just a few components you could select the pads individually and change the pad size with zero expansion, that's certainly possible as long you don't expand the pads too large to create a potential clearance problem. Copper-copper clearance could be pretty tight compared to solder mask slivers.
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Thank you!
You bet!
Awesome video!!
Truly excellent video. Thank you so much!
Thanks Alexander!
I'm dealing with solder mask expansion issues on a BGA with a fabricator right now, and this really helped me understand what they are asking for. These detailed fab tutorials are SO helpful. Thank you!
Happy to help
Good video. At my work we set expansion to 2 mils and minimum sliver to 4 mils. When a minimum sliver violation is triggered (fine pitch components) we manually remove the solder maks in Altium. It is better to don't have the solder mask rather than having to scrape the PCB between pads removing incomplete solder mask.
Of course, care must be taken when soldering those components, but there is no way around the PCB fabrication capabilities limits
@@jorditribo94 I agree, this is definitely one of those times where fab and assembly are in competition with each other
I got some valuable information from your comment.
My issue is
Thanx for information. I am still not clear : what "MINIMUM" values should be used for SolderMaskExpension and MinimumSolderMask Sliver ?
The real problem come , when one, use a Microcontroller with 100 pins.
I am using ATMEGA2560 , pad size is 11.2mil (.28mm)... SolderMaskExpension default Value is 4mil.
I am getting Design rule errors. Errors goes if I keep "MinimumSolderMask Sliver" VALUE to 0.8mil.
Please let me know the real practical values in my case.
Shall I reduce SolderMaskExpension Value to 2mil or 1 mil ?
and
Increase "MinimumSolderMask Sliver"
I really like their delivery of this kind of videos. Very casual discussion, not too formal and serious but freakin super informative and real world. Thanks man!
I have faced such kind of problem because of less sliver value.
Thank you Jack for explaining everything in detail.
Always welcome
Another thing is to set the layer colours I think is very important, working on Altium for years, Red on the top layer gives a lot of eye strain. I use a very light/pale green colour which is easy on the eyes, people can try which ever they think is good for them. Hope this helps.
Thanks for sharing!
Good point, hope in the next version altium will definitely address it.
I appreciate the thermal example at 13:33. I know it isn't the point, but it did make things more clear for me, because the surrounding copper fill instead of a trace was a concrete reason to need it.
Nice discusstion.
OMG first?!
This is where knowing your fabricator's registration capabilities becomes paramount. Design within them and Bob's your auntie. For those of us who go to the rapid prototyping fabricators, this has to include choosing component footprints that won't challenge their capabilities.
Another consideration is if you need to route traces under the solder mask slivers between pins.
Routing between pins under solder mask slivers was where this first came up for me. Doing a really dense board, some of the components are so close that you had these small slivers all over the place. Fab guys just said "over 5 mil slivers preferred" and that was their only guidance.
Thanx for information. I am still not clear : what "MINIMUM" values should be used for SolderMaskExpension and MinimumSolderMask Sliver ?
The real problem come , when one, use a Microcontroller with 100 pins.
I am using ATMEGA2560 , pad size is 11.2mil (.28mm)... SolderMaskExpension default Value is 4mil.
I am getting Design rule errors. Errors goes if I keep "MinimumSolderMask Sliver" VALUE to 0.8mil.
Please let me know the real practical values in my case.
Shall I reduce SolderMaskExpension Value to 2mil or 1 mil ?
and
Increase "MinimumSolderMask Sliver"
The solder mask sliver value should take precedence, and the specific value that your fabrication house will guarantee is placed correctly will depend on their capabilities. Typically the minimum value is 5 mil, but some fabrication companies can do smaller than that. Solder mask expansion should be smaller than the default value, I usually use 1 mil so that this allows for a very small amount of misregistration when the stackup is being built. If you are using a BGA footprint with oversized pads, you can apply a negative mask expansion so that you have a solder mask defined pad.
Hi Zach - Altium reports minimum sliver violations but it doesn't report an error when the sliver is zero or less i.e. when components are located close together. This could lead to manufacturing problems if the solder bridges between pads. Is there a way to setup a design rule to detect when there is no mask clearance between pads of different surface-mount components?
As long as there is some solder mask sliver (greater than 0 mil thickness), then you will be able to see the solder mask sliver rule will violation if you run a rules check manually. It just might not show the cue visually in the same way it does with copper-to-copper violations.
If you put two components so close together that the expansion totally removes the solder dam between the two components, then the dominant rule will now be the component clearance and not the solder mask sliver thickness. So let's say for example you set 2 mil minimum sliver with 3 mil expansion per pad by default, and let's say you set the pad-to-pad clearance to 10 mils. If you put two component pads near each other with 6 mil or smaller spacing, I've found you only trigger the clearance rule but not the sliver rule.
Hopefully that makes sense; the solder mask sliver rule only triggers if there is some solder mask sliver that exists between two pads, so if you eliminate it with expansion then the only relevant rule is the clearance and not the solder mask sliver.
Nice video!
We once had a problem with an electrolyte cap whose pad detached from the PCB (delamination?). I think the solution was to create a bigger pad and have a negative solder mask expansion so that the solder mask stops the pad from detaching. Is this a valid approach?
When did the delamination occur? Did this happen on an SMD cap during reflow or was this manually soldered? If it was manually soldered then your problem might be that the soldering tip is too hot. I've had this happen on small pads when hand soldering small components. If it's during reflow then that is pretty unusual, I've never seen that happen. You could use a bigger solder mask defined pad, but I'm not sure how much larger the pad needs to be to get greater adhesion, but it should scale linearly (double the pad area = doiuble the adhesion strength).
@@Zachariah-Peterson Thank you for the answer. I think it happened after reflow during transportation, the electrolyte capacitor was about 10mmX10mmX10mm big. In my opinion it is very unusual, especially if the board was only heated once for reflow and didn't go through any additional thermal cycling.
Interview questions 😳
I understand why a manufacturer or fabricator might want to apply positive expansion to correct for likely errors in their process. I understand why the original designer would want to specify negative expansion, to mechanically hold the pad on. But why would the designer specify positive expansion, instead of just making the pad a little larger? Are thermal relief requirements that tight? Is the copper-copper clearance typically more than the minimal mask sliver size, and they're just trying to minimize the adjustments made later by the manufacturer?
In my opinion, just from a practical standpoint, it's a lot easier to change the expansion than it is to change all the pads in your footprints. If you're downloading your footprints, those pad sizes are already set, but you can really quickly change the mask expansion for all the components in the design rules. If it's just a few components you could select the pads individually and change the pad size with zero expansion, that's certainly possible as long you don't expand the pads too large to create a potential clearance problem. Copper-copper clearance could be pretty tight compared to solder mask slivers.