Hi Zach, great video and great symbols! I have recently designed a prototype board with a wifi controller on it. The prototype is relatively large and when you bend the pcb, theres noise on the GPIOs. Can this come from parasitic capacticances in the stackup? The microcontroller as well as two dc/dc converters are mounted via their own small carrier pcb, so another reason might be poor soldier connections while bending the board. Thanks in advance an keep up the good work!
Hi Adrian, Thanks for watching, I don't want to make a definitive statement about that without looking at a stackup, but it might be due to some capacitive coupling between GPIO lines and some other circuit that switches at high frequency. Switching regulators will have a high dV/dt node on them that can couple noise to different areas of the board during switching. There's actually an older app note from Linear that specifically discusses that point about switching regulators: www[dot]analog[dot]com/media/en/technical-documentation/application-notes/an136f.pdf Also, why are you trying to bend the board?
@@Zachariah-Peterson Thank you for the answer, I will look into the app note and take another look at my dc/dc converters. Actually I am not trying to bend the board, but I have difficulties telling my software coworker to handle the electronics more delicately.
@@Zachariah-Peterson The board had some more problems. The MCU turned off under shock or vibration. It turns out, the GND pads between the carrier board and the main PCB were not soldered properly and were still paste to some part. Through the flexing of the PCB the MCU's GND pins lost contact or had some Ohm connectivity.
Can we simulate parasitic elements of the digital part of board with spice ? For example, the circuit between cpu and ddr3 including digital buses and traces.
Yes you can, you just need to set a voltage source as a square wave with a specific edge rate. You could then look at how the parasitics degrade edge rate or how the edge rate might excite resonances. In SPICE, you won't have any ability to simulate transmission line propagation unless you have a transmission line model. There were models in an old Altium library in AD21, I do not know if that is still around in AD24.
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Thank you, Dr. Peterson!!!
Thanks for the video
what can be the magnitude of parasitic inductance, capacitance?
Typically nH for inductance and pF for capacitance.
Hi Zach, great video and great symbols! I have recently designed a prototype board with a wifi controller on it. The prototype is relatively large and when you bend the pcb, theres noise on the GPIOs. Can this come from parasitic capacticances in the stackup? The microcontroller as well as two dc/dc converters are mounted via their own small carrier pcb, so another reason might be poor soldier connections while bending the board. Thanks in advance an keep up the good work!
Hi Adrian,
Thanks for watching, I don't want to make a definitive statement about that without looking at a stackup, but it might be due to some capacitive coupling between GPIO lines and some other circuit that switches at high frequency. Switching regulators will have a high dV/dt node on them that can couple noise to different areas of the board during switching. There's actually an older app note from Linear that specifically discusses that point about switching regulators: www[dot]analog[dot]com/media/en/technical-documentation/application-notes/an136f.pdf
Also, why are you trying to bend the board?
@@Zachariah-Peterson Thank you for the answer, I will look into the app note and take another look at my dc/dc converters.
Actually I am not trying to bend the board, but I have difficulties telling my software coworker to handle the electronics more delicately.
@@Zachariah-Peterson The board had some more problems. The MCU turned off under shock or vibration. It turns out, the GND pads between the carrier board and the main PCB were not soldered properly and were still paste to some part. Through the flexing of the PCB the MCU's GND pins lost contact or had some Ohm connectivity.
Can we simulate parasitic elements of the digital part of board with spice ? For example, the circuit between cpu and ddr3 including digital buses and traces.
Yes you can, you just need to set a voltage source as a square wave with a specific edge rate. You could then look at how the parasitics degrade edge rate or how the edge rate might excite resonances. In SPICE, you won't have any ability to simulate transmission line propagation unless you have a transmission line model. There were models in an old Altium library in AD21, I do not know if that is still around in AD24.
@@Zachariah-Peterson Thank you so muck Mr. Petersom. How can i have these models ? Frim where ?
11:30
you inductors symbols need more security procedure, cause it look like a cloud! xD