Thumbs up for the awkward jokes! Hope you enjoyed watching this video! Feel free to leave a comment if you have any questions or just want to say hi!!😄
As the channel name suggests, this lesson was really simple and helpful. Thanks for it, other tutorials about this topic were either too complicated or were lacking depth
Typically, you can look into FPGA boards based on what Peripherals are included - that will be a some sort of limitation of how large projects you can do. Also # ofCLBs in an FPGA can determine how big of a project you can actually do.... you do have limited amount of space. So, those might be some key things you would want to keep an eye out for, maybe there are some other people out there who read this, they might be able to give some extra information to you as well! Best of luck, thanks for being part of this community!
Alex, you are absolutely correct, the clock in an FPGA is 50% duty cycle just like the one in CPU or many other devices out there. Thanks for the question!
Generally the clock is not gated. To prevent the flip-flop from changing, you would add a 2:1 selector. In the hold case, feed the Q output back to the D input. In the load case, feed the input to D.
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Thumbs up for the awkward jokes! Hope you enjoyed watching this video! Feel free to leave a comment if you have any questions or just want to say hi!!😄
The Flip Flops :) 🥿🥿
As the channel name suggests, this lesson was really simple and helpful. Thanks for it, other tutorials about this topic were either too complicated or were lacking depth
Great way of sharing knowledge among fpga enthusiasts👍🏼👍🏼
Loved your tutorial
Keep making these kinds of videos 🥰🥰
Explained it so well thanks
Thank you
sir, can you tell about different fpga boards and difference between them.Which is good for small projects and which is good for large projects.
Typically, you can look into FPGA boards based on what Peripherals are included - that will be a some sort of limitation of how large projects you can do. Also # ofCLBs in an FPGA can determine how big of a project you can actually do.... you do have limited amount of space. So, those might be some key things you would want to keep an eye out for, maybe there are some other people out there who read this, they might be able to give some extra information to you as well! Best of luck, thanks for being part of this community!
very useful, many thanks
The clock cycle in FPGA is no different than the clock cycle in a standard CPU, correct?
Alex, you are absolutely correct, the clock in an FPGA is 50% duty cycle just like the one in CPU or many other devices out there. Thanks for the question!
What are you using for timing diagrams? They look like Wavedrom.
Very helpful!
Thumbs up tutorial
Why would you use a flip flop? I assume you can use it as storage, but you would need to stop the clock using a switch or something?
Generally the clock is not gated. To prevent the flip-flop from changing, you would add a 2:1 selector. In the hold case, feed the Q output back to the D input. In the load case, feed the input to D.
JK flip flops used to make a binary counter......how the fpga can make a counter with D flip flops ???
I don't know what this is.
I know it's not accounting it's not engineering it's not economics it's not biology. I don't know what this is