Sir, Could you please explain this error in the Layout: P+ emitter size by 10 um must touch a substrate PW strap guard ring. This must surround the NW strap guard ring.
A small correction here. LUP.6 does not imply that source or drain area should be greater than 30um. Rather it implies that the source and drain should have a tap such that every point of source/drain area sees the tap within 30um of distance. This comment is about the video clip from 7.30 to 8.00
in this video , i'm just showing how & by what name we will get latch up error , i'm not covering so deeply with that DRC error , Thx for your comment ...
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Sir, Could you please explain this error in the Layout:
P+ emitter size by 10 um must touch a substrate PW strap guard ring. This must surround the NW strap guard ring.
A small correction here.
LUP.6 does not imply that source or drain area should be greater than 30um. Rather it implies that the source and drain should have a tap such that every point of source/drain area sees the tap within 30um of distance.
This comment is about the video clip from 7.30 to 8.00
in this video , i'm just showing how & by what name we will get latch up error , i'm not covering so deeply with that DRC error , Thx for your comment ...
Sir how to open the calibre and why ?
What ? Your question
not a 600u what you said please say 600n size of NMOS .
Some time I may say wrong value , cos I can't follow the tool & device value in same time