How latch up will take place - English Version

[@bhanuprakash6610]

I am watching u r vedios from the last week .....vedios are really nice ....with good explanation and presentation.....thank u for up loading latchup once again.......do more and more videos

[@analoglayout]

sure

[@pratikmori]

NPN and PNP transistor emitter pin arrow marking are inverted.
For PNP transistor it should be inside and
NPN transistor it should be outside.

[@anilkumarkurra1314]

Thank u for u r videos and it is really helpful

[@nandhinisubramani9273]

very clear explanation.thank u sir

[@successpage6866]

Sir , I have a doubt sir , adding tap cell for avoiding the latch up. But then why p &n tap is helping it to formation of latch up.

[@analoglayout]

I didn't get your question

[@successpage6866]

@@analoglayout sir , We are adding Tap cell for prevent the latchup problem. But you taught bulk of NMOS and NMOS source act as forward bias , it will flow the current .So my question is Why Tap is helping to create a latch up problem.

[@gokulnathl4530]

how the leakage will collect by tap cells in PMOS and NMOS? pls explain

[@successpage6866]

Same doubt ,I am also Gokul

[@eslavathswetha3942]

Hi, at the point of 8:08 the voltage at vss will be 4.3 not -0.7 please check

[@raviraju9018]

Vss connect with ground so -0.7

[@imhareesh9096]

Is transistors are in which configuration 👉CB or CE configuration??

[@chethanjavoornanjappa]

getting very confused in this video

[@Anjay17680]

sir , please tell us how tap cell is placed to overcome latch up problem?

[@The_dimple_girl_]

Why does the drain fall below ground Voltage

[@analoglayout]

Suppose , if u get any reverse or leakage from drain , cause by other devices . So it's a situation , it may happen , may not , but we are studying what if happen

[@burrivenkatesh4480]

Sir why resistor is only connected to base not connected to collector or emitter plz tell me one interviewer asked me this question

[@jsjcho2923]

That may be because taps for the bulk may be far away from the junction and resistance in the path is more which is the reason for latchup happening.

[@nehathakur3772]

Direction of transistors arrow is wrong

[@analoglayout]

if its wrong , correct it by your self

[@surajsingh-nx6zl]

Hahaha savage

[@karthigaivallikv8439]

transistor arrow is correct,,, pls see again

[@siddhantchouksey]

transistors arrow is incorrect

[@TharunPramod]

Arrows are incorrect

[@successpage6866]

Adding Tap cell is for avoiding the latch up. Then how it will helpful for latch up sir. This is my doubt sir.

[@nareshvennapusa6454]

Directions are misguiding...... chanage it