Just 35 seconds into your video and I already subscribed. You have a very pleasant voice and pace, and a clear way of explaining. Thank you for your efforts.
I had to watch this a bunch of times but I got a version to work, with indentation and longer more descriptive variable names. One thing that had me stumped me for a bit was that the PLL setup just crashed every time I tried to run it. I ended up writing a simple clock divider module to divide the 50MHz clock down to 3.2 MHz, it happens to be integer divisible, so the PLL is really overkill when synchronization is not needed. Thanks for the detailed tutorial a learned a bunch trying to get this to work.
I had the same problem on arch linux. This bug can be circumvented by first increasing the size of the megafunction settings window so that all the information fits on it (without scroll bars)
The timing diagram goes from 1 through 16, while count goes from 0 through 15. Perhaps “if (count ==1)” should be “if (count == 0)” since that is the beginning of the counting.
@@gregbushta3086 I was shouting at the screen every time I saw count == 1 as the start point of the logic!!! It should be all be working on a count of 0 to 15, not 1 to 16!
Thank you for the amazing material! What kind of BNC adapter/setup are you using to connect the Function Generator's output to the de0-nano PMOD? Also, would you recommend getting de0-nano or de10-nano?
Hi, there's no connector - just simple jumper wires into the header pins of the DE0 and crocodile to BNC to the function generator. I haven't used the DE10 nano yet but it looks like a superior board to the DE0 and has the advantage of the Cortex embedded cores integrated into the same chip. The DE0-nano is limited also by relatively few logic elements, so it fills up pretty quickly. All things considered, I would recommend the DE10-nano as the best board to get in that price range!
@@VisualElectric_ Thank you! Actually ended up getting myself a DE10-Nano kit from DigiKey few days ago, so I want to try making similar project to yours! Curious if you will be covering more of the (FPGA Cortex HPS) inner communication via Avalon interface at some point? Or things like Ethernet, clock domain crossing, thanks again!
If I understood well (in minute 35), you are sending by 'din' the channel address 3'b 010 (=2) but 'dout' in the analyzer is the result of sampling Channel 0 ??
hello sir and congratulations on your great video. I try to implement an spi for cyclone ii but it doesnt work right and i am desperate for help. Could I email you for further questions?
Hello Sir, thanks a lot for this excellent video ! 😁 I work on the DE0-Nano board and I am trying to add the multiplexing of the 8 channels of the ADC to your code. But it doesn't work ! Can I send you my project files so that you can correct it ?
Just 35 seconds into your video and I already subscribed. You have a very pleasant voice and pace, and a clear way of explaining. Thank you for your efforts.
It's really an exhaustive explanation of the SPI interface for peripherals to the Cyclone IV.
Keep making them, Awesome !!
Love practical FPGA ADC interfacing
Thankyu sir ... waiting for your more videos on different topic of FPGA
I had to watch this a bunch of times but I got a version to work, with indentation and longer more descriptive variable names. One thing that had me stumped me for a bit was that the PLL setup just crashed every time I tried to run it. I ended up writing a simple clock divider module to divide the 50MHz clock down to 3.2 MHz, it happens to be integer divisible, so the PLL is really overkill when synchronization is not needed. Thanks for the detailed tutorial a learned a bunch trying to get this to work.
I had the same problem on arch linux. This bug can be circumvented by first increasing the size of the megafunction settings window so that all the information fits on it (without scroll bars)
Very nice tutorial 👌
Thanks for this great video! There's just one thing. I think count on line 82 (44:39) will never get into case 16 since it is a 4bit register.
So, is there a workaround which would let me get better resolution? Any changes recommended?
The timing diagram goes from 1 through 16, while count goes from 0 through 15. Perhaps “if (count ==1)” should be “if (count == 0)” since that is the beginning of the counting.
@@gregbushta3086 I was shouting at the screen every time I saw count == 1 as the start point of the logic!!! It should be all be working on a count of 0 to 15, not 1 to 16!
One of the best videos. Thanks
Super explanation..👍
Sir can I use this code for DE10LITE in quartus prime FPGA?
I've never used the DE10-Lite, but it does have an integrated ADC. There's an example in the demonstration folder in the user documentation.
You are an absolute top man 💪
Thank you for the amazing material!
What kind of BNC adapter/setup are you using to connect the Function Generator's output to the de0-nano PMOD?
Also, would you recommend getting de0-nano or de10-nano?
Hi, there's no connector - just simple jumper wires into the header pins of the DE0 and crocodile to BNC to the function generator. I haven't used the DE10 nano yet but it looks like a superior board to the DE0 and has the advantage of the Cortex embedded cores integrated into the same chip. The DE0-nano is limited also by relatively few logic elements, so it fills up pretty quickly. All things considered, I would recommend the DE10-nano as the best board to get in that price range!
@@VisualElectric_ Thank you! Actually ended up getting myself a DE10-Nano kit from DigiKey few days ago, so I want to try making similar project to yours!
Curious if you will be covering more of the (FPGA Cortex HPS) inner communication via Avalon interface at some point? Or things like Ethernet, clock domain crossing, thanks again!
Pls use some code formatting. That cs?1:clk blow my mind
Why do you not take timings in your consideration mentioned in timing diagram
If I understood well (in minute 35), you are sending by 'din' the channel address 3'b 010 (=2) but 'dout' in the analyzer is the result of sampling Channel 0 ??
hello sir and congratulations on your great video. I try to implement an spi for cyclone ii but it doesnt work right and i am desperate for help. Could I email you for further questions?
Can you please show the connection you did on the board.
Hello Sir, thanks a lot for this excellent video ! 😁 I work on the DE0-Nano board and I am trying to add the multiplexing of the 8 channels of the ADC to your code. But it doesn't work ! Can I send you my project files so that you can correct it ?
design and implemntation of spi protocal using veilog Hdl is this board or other board is avilable sir
thanks a lot
Thank you so much...can u plz provide the code??
Did he provide the code? xd
hai can you upload the verilog code?
Did you ever hear of indentation?
what if we want to operate in three channels, how do we proceed with the code?
I used the same `timescale command but it is not working
hello sir where can learn verilog for perfect implementtion
Tutorials point and TH-cam playlist
👍
Dear author, Can you please share me the source codes? github link or something like that, thank you so much.
31:50 terrible display, you could have minimized the timing diagram on the left half of the screen.
Sir, is there any document related to this video , if so plz can you share it with me.
Thank you sir