would be nice if you could explain the hold and setup times more instead of just repeating the same thing about the delay, which is honestly pretty self explanatory
It is not required for the calculation of maximum clock frequency. I have already covered it from 6:10 onwards. The only thing which we need to check is, there should not be hold time violation. In this case it is not happening. Because the propagation delay from FF1 to FF2 is 7ns, while the hold time of FF2 is 3ns. That means Tpd > Th. Similarly, the propagation delay from FF2 to FF1 is 8ns, while the hold time of FF1 is 1ns. So, once again there is no hold time violation. I hope, it will clear your doubt.
In this case, if you see the propagation delay of the flip-flops or even the logic gates (2ns + 2 ns), it is more than hold time. That means there won't be any hold time violation in any flip-flop. And as I said in the video, for the calculation of minimum required clock frequency, we do not need hold time. Just we need to ensure that there is no Hold-Time violation. Please check at 11:20.
14:09 in starting first case u are considering only propagation delay of the first flip flop why didnt you consider the setup time in starting but after one reputation u r considering the setup time of the first flip flop
At first, we were calculating the minimum required clock for the second flip-flop. So, in that case there is no need to consider the setup time of the first flip-flop. In that case, we have considered to total propagation delay from the FF1 to FF2 plus the setup time of FF2. In the second case, when we are calculating the minimum required clock for FF1, then the setup time of first flipflop is considered. Please check that example once again, you will get it. And if you still have any doubt then let me know here.
I have already made video about SRAM, DRAM and different memories. Please go through technology playlist on the channel. You will find it. In case, if you didn't get, let me know here. I will send you a link.
It is the minimum clock duration. That means Tclk can be more than 13 ns, but it cannot be less than 13 ns. If it is less than 13 ns, then there will be timing violation.
Thank you for the video, but your inflection on the ends of the sentence where you bring your voice up and then pause to monotonously say the last word is very distracting. Please just use your normal voice. I mean no offense or anything, and I know English isnt your first language. Thank you again!!
For more videos on Digital Electronics, check this playlist:
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Could you do a session on counters? Your videos are so helpful ☺️
Yes, it will also be covered soon.
Thanks, this was asked in an AMD interview on campus !!!
God bless you thanks
clarity and clean explanation throughout the video. Thanks.
THANKS FOR SUCH A WONDERFUL VEDIO
would be nice if you could explain the hold and setup times more instead of just repeating the same thing about the delay, which is honestly pretty self explanatory
Explained very efficiently
I love you
You are the BEST
wonderful :D
I understood some problems very useful
Really thank you, it helps me very much,
@15:00 why are you not considering the Hold times that are given?
It is not required for the calculation of maximum clock frequency. I have already covered it from 6:10 onwards. The only thing which we need to check is, there should not be hold time violation. In this case it is not happening. Because the propagation delay from FF1 to FF2 is 7ns, while the hold time of FF2 is 3ns. That means Tpd > Th. Similarly, the propagation delay from FF2 to FF1 is 8ns, while the hold time of FF1 is 1ns. So, once again there is no hold time violation.
I hope, it will clear your doubt.
thank you!!!!!
Thanks sir
Hi Sir, In your last example , why didnt you consider Th into your calculation at all?
In this case, if you see the propagation delay of the flip-flops or even the logic gates (2ns + 2 ns), it is more than hold time. That means there won't be any hold time violation in any flip-flop. And as I said in the video, for the calculation of minimum required clock frequency, we do not need hold time. Just we need to ensure that there is no Hold-Time violation. Please check at 11:20.
@@ALLABOUTELECTRONICS Thanks sir
14:09 in starting first case u are considering only propagation delay of the first flip flop why didnt you consider the setup time in starting but after one reputation u r considering the setup time of the first flip flop
At first, we were calculating the minimum required clock for the second flip-flop. So, in that case there is no need to consider the setup time of the first flip-flop. In that case, we have considered to total propagation delay from the FF1 to FF2 plus the setup time of FF2.
In the second case, when we are calculating the minimum required clock for FF1, then the setup time of first flipflop is considered. Please check that example once again, you will get it. And if you still have any doubt then let me know here.
What is sampled you mean the read and write....
Yes, the Flip-Flop reads the input at the clock edge.
Very nice 👌👌👌
Please make detail video on MCU & MPU and Memory (DDR1-4 & Flash) and Ethernet
I have already made video about SRAM, DRAM and different memories.
Please go through technology playlist on the channel. You will find it.
In case, if you didn't get, let me know here. I will send you a link.
Thank you
Even there Will be a clock delay for first and second flop right??
Yes, a clock skew.
If TPLH and TPHL delay are different for a waveform, then what will be the actual delay?
If both are different then generally the average of both delay is considered.
setup time is how much before of the arrival of the clock edge ?
That information would be specified by the data sheet of the device.
CHICLAYO PERU 🇵🇪 💵 🔱
Make video on BCA questions solving
There is already a seperate channel for Quiz. Please check the second channel ALL ABOUT ELECTRONICS - QUIZ.
You mean 8 + 5 is the maximum clock duration, not minimum right?
It is the minimum clock duration. That means Tclk can be more than 13 ns, but it cannot be less than 13 ns. If it is less than 13 ns, then there will be timing violation.
greaaattttttt
i will send problem to you ,can you give solution for the problem ?
This lecture is difficult to understand for me. May be of new terms, words 🤔🤔
Thank you for the video, but your inflection on the ends of the sentence where you bring your voice up and then pause to monotonously say the last word is very distracting. Please just use your normal voice. I mean no offense or anything, and I know English isnt your first language. Thank you again!!
Nai samaj me araha😭