but sir isn't the combinational circuit used in 4 bit register is actually a 2x1 mux??? it will be easy for all to understand the load operation through mux circuit instead of combinational circuit.
Here I was referring to the propagation delay in the clock signal. when you apply the clock through the AND gate then clock signal to the register will get delayed.(Its called clock skew, I will cover that in the very next video). And it can cause synchronization issue in the large digital circuits. So, here instead of doing that, the clock signal is applied directly. And the combinational logic is implemented in the data path. Of course, these additional AND and OR gates will increase the propagation delay in the data path. (Flip-flop will receive the input after finite propagation delay). But as far as the inputs satisfy the setup and hold time condition of the flip-flop, it will not make much difference.
That is how the results are stored. When the load is low, then Q will be connected to the D input of the flip-flop and the flip-flop will retain the same state. Please check at 6:17.
In the subsequent videos of the register, I have already explained it. Please check the recent video. In that, D flip flops have been used. But you can use jk flip flop also. Just use JK flip flop as D flip flops. Basically you just need to apply the input to J input of the flip flop as it is, while the same input should be applied to K input of the flip flop via NOT gate. In the flip flop conversion video, I have covered that. Please check this video for more info: th-cam.com/video/bl77FRTAXWA/w-d-xo.html
You need to stop with that weird intonation at the end of sentences. Try just speaking the whole sentence in the same intonation as you do on the start :)
![ลองสุ่มไอโฟน 990 โกงมั้ย? [ โกงมั้ยครับ ep.101 ] | DOM](http://i.ytimg.com/vi/bfsWe0j492k/mqdefault.jpg)
![[MV] A leap of faith...ความเชื่อใจครั้งสุดท้าย (From "Petrichor the series")](http://i.ytimg.com/vi/U1piZH2CNXA/mqdefault.jpg)
For more videos on Digital Electronics, check this playlist:
bit.ly/31gBwMa
best explanation as usual 👍🏻
Absolutely superb
Superb explanation
V. Nice 👍
Very nice 👌👏👏👏
but sir isn't the combinational circuit used in 4 bit register is actually a 2x1 mux??? it will be easy for all to understand the load operation through mux circuit instead of combinational circuit.
Yes, I am going to link that in the upcoming videos, when I will discuss the universal shift register.
Good 👍
sir how are we saving propagation delay when we are using so many gates instead of simply a and gate in 4 bit register
Here I was referring to the propagation delay in the clock signal. when you apply the clock through the AND gate then clock signal to the register will get delayed.(Its called clock skew, I will cover that in the very next video). And it can cause synchronization issue in the large digital circuits. So, here instead of doing that, the clock signal is applied directly. And the combinational logic is implemented in the data path. Of course, these additional AND and OR gates will increase the propagation delay in the data path. (Flip-flop will receive the input after finite propagation delay). But as far as the inputs satisfy the setup and hold time condition of the flip-flop, it will not make much difference.
the intonation at the end of each sentence is driving me crazy , i cant even focus on the video because i keep skipping it , great explanation tho
lol me too literally every sentence
Cant we connect D and Q directly and store the results
That is how the results are stored. When the load is low, then Q will be connected to the D input of the flip-flop and the flip-flop will retain the same state. Please check at 6:17.
If we connect B D AND Q then do we need to keep a separate load line@@ALLABOUTELECTRONICS
Emotional news: cash coming back to you
4 - Bit Register using JK Flip Flop with Paralle load Circuit ?
🙏🙏🙏🙏🙏🙏
In the subsequent videos of the register, I have already explained it.
Please check the recent video. In that, D flip flops have been used. But you can use jk flip flop also. Just use JK flip flop as D flip flops. Basically you just need to apply the input to J input of the flip flop as it is, while the same input should be applied to K input of the flip flop via NOT gate. In the flip flop conversion video, I have covered that.
Please check this video for more info:
th-cam.com/video/bl77FRTAXWA/w-d-xo.html
@@ALLABOUTELECTRONICS Ok got it. Thanks you
sir, samajh nhi aaya.
Konsa part samajh nahi aya ?
You need to stop with that weird intonation at the end of sentences. Try just speaking the whole sentence in the same intonation as you do on the start :)
It's definitely an ESL thing, but agreed - it distracts from what is otherwise an awesome explanation.
I agree that could be distracting sometimes but as the other guy its probably result of ESL
What is ESL?
Yeah what's ESL?
english second language
most annoying accent unfortunately. The information is great