animating STA concept just enhanced the ingrasp nature and understandibility of the topic..and i know it would have taken lot of time to do this brother....thanking u from bottom of my heart.
Seriously I don't know what exactly STA means, through this videos I wanna thank Yash Jain from my bottom of my heart❤️ for providing this videos with good explanation and making it well clear.
Very nice explanation sir. Thank you so much for making this available for all. Sir could you please tell me... In which software you are preparing these videos please.
while explaining the hold time violation at last 5.28 if u advance the Din then will it not give setup time violation??? because it falls under the 1us of setup time.
hi sir, Is there way to understand intuitively as to why setup and hold time will increase in case there is delay at D and Clk pin in a system? I get the math but is there someway to get the feel as to why?
If you want get a feel, see it like a race between the clock and data, both are required to reach the flop at a particular time wrt each other, but if there are any hurdles in their path, definitely it will affect(not necessarily increase) the S/H times.
Negative is not something absolute, but relative to a particular instant that we denote as zero(for example if we take the current clock edge to be arriving at time t=0, then anything before that we can consider negative and anything after that to be positive). Its all relative!!
To anyone watching this video, please please finish off the playlist. The way he has built on the concepts is amazing!
animating STA concept just enhanced the ingrasp nature and understandibility of the topic..and i know it would have taken lot of time to do this brother....thanking u from bottom of my heart.
I congratulate you on the motto set by you to empower Semiconductor Industry by giving industry-required knowledge to the students.
Thanks Sourav
Its the best videos for STA on youtube
You have explained it very clearly. Thank you for the video!
This is one of the best STA video i have ever seen.kudos
Thanq
After watching this video ,I'm confident enough to give any interview for digital electronics. 🙌 Sir please help us with analog electronics as well.
Sure, I'll be making them after completing the digital concepts
Seriously I don't know what exactly STA means, through this videos I wanna thank Yash Jain from my bottom of my heart❤️ for providing this videos with good explanation and making it well clear.
My pleasure 😊
It did help me to shift my domain from software to digital, thank you.. nice video :)
Glad, it helped you. That's my only purpose
How did you get that equation for hold and setup times?
Sir make video on how to bear electronics. Pls sir. Great video sir
Thank you so much. And don't worry, I am here to make it easy and bearable for you all.
You explained this concept so easily. Thank you so much sir😍
Animation absolutely underrated my brother 💥
Really amazing video....well designed...
Thanks bro, the best basic knowledge video on youtube about STA
Nice Yash! It was a good video! Perfect speed, example, animation, clarity, and font!
Glad you liked it
Amazing job! All the best!
how did you consider 1ns for setup time when td>tc?
Thank you so much sir, your lectures were very helpful to me
So Helpful 🤟
Very well explained through timing graphs. I wish you could have made this video a year ago.
Haha, you've got offline sessions instead :p
Very helpful !!
Really nice video!
Thank you, more videos coming soon
Well explained..great effort 🤩
Well explained ! 👍🏻😅
Very nice explanation
Thanks Ajith !!
Nicely explained!
Thank you for the explanation sir.
Very well explained Sir✨
So helpful and well explained
Thanks for watching, more videos coming soon
Hi sir.. U r just amazing.. Please cover more on sta ..we are waiting
Thanks Rajashree, more content on the way !!
outstanding
Thank you for this knowledge sharing 🙏
Precise and well explained! Could you please suggest some resources which you referred to learn STA. Thank you.
could you please make the continuation videos? I am awaiting the lectures. please it is a suppliant solicitation to upload the sequel
Next Video coming today!!
amazing
Amazing!!
Amazing explanation! :DD
Glad it was helpful!
This is great🤩🤓
Thank you so much, stay tuned for complete series.
Great initiative, Yash! Super proud! 😁
All credits to you mam, won't be possible without your guidance 🙏
Well explained and simplified :)
Thank you so much mam for your support and guidance.
Well done buddy.. Good going 👍
Thank you bro, means a lot
Does adding mux creates more area than adding pipelined register?
At 4:26
Why only setup is checked
Why not hold is checked, sir?
and vice versa at 5:22
This is awesome! It would be great if you can do some example problems on this topic
Thank you so much Manasa, sure I'll be making example videos. Sorry for the delay.
@@therisingedge Hi Yash.. Thank you so much for this info..could u pls make some beneficial videos for students on analog as well ?
Can you share some reference book from where we can prepare for internships in digital electronics.
Sir you told Td=3ns but D will be activated at 1.5ns only why?
But Tc activated exactly at 2ns
How to address if it is both setup and hold critical?
sir, please recommend some questions for practice
My blog is coming soon. There you'll get practice problems to solve. Hope that helps :)
@@therisingedge Could you please tell your blog name
Very nice explanation sir.
Thank you so much for making this available for all.
Sir could you please tell me... In which software you are preparing these videos please.
Sir If possible can you please provide the notes of complete STA vedios
while explaining the hold time violation at last 5.28 if u advance the Din then will it not give setup time violation??? because it falls under the 1us of setup time.
Thank you very much and well done for your explanation. Can you give any pdf for that?
Can you provide the pdf of these notes, please? It's amazing.
Sir ur video is very helpful for me, keep posting such kind of videos, waiting for more 👍
Sure, more videos coming soon. Thank you so much for watching
hi sir, Is there way to understand intuitively as to why setup and hold time will increase in case there is delay at D and Clk pin in a system? I get the math but is there someway to get the feel as to why?
If you want get a feel, see it like a race between the clock and data, both are required to reach the flop at a particular time wrt each other, but if there are any hurdles in their path, definitely it will affect(not necessarily increase) the S/H times.
@@therisingedge ok thanks for a quick response
Why did you draw data like that going up and down at the Same time with many lines although the clock just goes high and low in a row
Is it right to take time in negative
Negative is not something absolute, but relative to a particular instant that we denote as zero(for example if we take the current clock edge to be arriving at time t=0, then anything before that we can consider negative and anything after that to be positive). Its all relative!!
Hope that clears your doubt.
@@therisingedge yes I understand thanks man
I don't understand the Din and D concepts
TY Sir for this superb content, Just a doubt , why hold time is not discussed for case 1?
pta chale to batana
At least one among Setup or Hold times exist Then metastability happens, so I guess it is the reason why sir didn't discuss Hold time in case 2.
Bro one group that is "vlsi for all" they are copied your slides exactly same.
4:36 I don't understand this
too fast
Don't understand anything
Pagal bna gya ye to 😂😂