Thanks for the video... I have a doubt.. Vt is increasing that is ok... But whats going on at the electron hole level that i wanted to under stand.... Why its increasing?... What happens for pmos and what happens for nmos at electron hole level.. How its affecting... If you have any idea about it? Thanks
Hi Sir. Thank you for the explanation. Sir, is there any tool that can be used to detect WPE issue? does the WPE issue is included in post-layout simulation (layout extraction)? you've mentioned that dummy is one of the methods to prevent WPE. how the dummy transistor can affect layout performance such as parasitic? I once saw the schematic has a lot of dummy transistors and the other schematic does not require a dummy transistor. what are characteristics that a circuit needs to have a dummy and how many dummies are actually needed for a circuit?
Hi Sir, Thank you for all your videos. I have questions. You have explained about PMOS only. But there is WPE rule which asks nmos to be spaced apart from NWELL edge. Can you please explain ? Thanks in advance . Keep up the good work.
at 8:04 minute you are saying Source current capacity is more than Drain, but in the plot, the drain capacity is reduced by -20% whereas the source capacity is reduced by -30%. This means the Drain current capacity is more than Source. isn't it? could you please explain this
At 8.04 min, I am discussing about Source and Drain oriented devices. So what I meant is if Source of the device is near to well or drain of the device is near to well, the effect will not be same.. Vt increase will not be same. Others are numericals to show systematic errors introduced. So the gist of the entire discussion is place devices away from the well edge..use dummies..else threshold voltage can increase by 30mv to little more than 100mv
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so appreciated of your sharing the knowledge of silicon semiconductor .
Nice video , S-oriented and D-oriented devices was a new concept to me.
Very nice vedio sir...thank u
Thank you sir, very short and useful
wonderful explaination .
Thanks for the feedback
Thanks for the video... I have a doubt.. Vt is increasing that is ok... But whats going on at the electron hole level that i wanted to under stand.... Why its increasing?... What happens for pmos and what happens for nmos at electron hole level.. How its affecting... If you have any idea about it? Thanks
Nice explanations, thanks
Hi sir thanks for your explanation
Could you please explain how vt of source oriented is different from drain oriented device?why vt would be same for source & drain oriented devices?
Hi Sir. Thank you for the explanation.
Sir, is there any tool that can be used to detect WPE issue? does the WPE issue is included in post-layout simulation (layout extraction)?
you've mentioned that dummy is one of the methods to prevent WPE. how the dummy transistor can affect layout performance such as parasitic?
I once saw the schematic has a lot of dummy transistors and the other schematic does not require a dummy transistor. what are characteristics that a circuit needs to have a dummy and how many dummies are actually needed for a circuit?
Hi, good questions. I will try to get answers for them soon.
Will this effect remain same for p well also, as here discussed about nwell
yes
thank u for this video sir, please make a video on short channel effects
Sure...I will cover all short channel effects
Very nice
good explanantion
Thanks
hi sir, please make video on STI AND LOD and please explain how does it effect
sure
Hi Sir, Thank you for all your videos. I have questions. You have explained about PMOS only. But there is WPE rule which asks nmos to be spaced apart from NWELL edge. Can you please explain ? Thanks in advance . Keep up the good work.
Hi sir ,I have a doubt in the sti effect why pmos current increases and nmos current decrease,can you clarify my doubts
Can you elaborate that
I have a doubt in wpe why pmos current is more compare to the nmos
I have explained only pmos in the examples. Pmos transistors are in nwell... wpe is for pmos transistors close to the well edge
@@analoglayoutdesign2342 For nmos devices placed close to nwell also can face similar issues ,right?
ions are already sitting in the well . So pmos has majority carriers as holes . so, settled ions will ease the mobility
Will NMOS device also get effected because of wpe?
Yes..it will also get affected
at 8:04 minute you are saying Source current capacity is more than Drain, but in the plot, the drain capacity is reduced by -20% whereas the source capacity is reduced by -30%. This means the Drain current capacity is more than Source. isn't it? could you please explain this
At 8.04 min, I am discussing about Source and Drain oriented devices.
So what I meant is if Source of the device is near to well or drain of the device is near to well, the effect will not be same..
Vt increase will not be same.
Others are numericals to show systematic errors introduced.
So the gist of the entire discussion is place devices away from the well edge..use dummies..else threshold voltage can increase by 30mv to little more than 100mv
How doping will change vt is my doubt
kindly go thru video again..its mentioned... when doping conc changes, vt changes