Why Layout Matching with the Same Unit Size & Dummy Devices ?

Hi all,
Thanks for @chieh-jutsai9026's good catch of my drawing mistake in the"Why Layout Matching with the Same Unit Size & Dummy Devices" video, and @hrachyakhachatryan1796 's good suggestion.
I"ve put the corrected circuit image of the OTA & Bias in the comments below. Thanks for everyone's understanding and I apologize for the oversight in my drawing again. There should be only one diode-connected VCSN here, not two before.
Thanks,
CC

[@circuitimage]

Hi all, thanks for Chieh-Ju's good catch. Here (drive.google.com/file/d/1Z9_N02j351MdXOzHHYm_zgSfPGFGOxpO/view?usp=share_link) is the correction circuit image of the OTA & Bias. Thanks for everyone's understanding and I apologize for the oversight in my drawing :(

[@hrachya_khachatryan]

Thank you for letting us know about the fix. Two suggestions:
1) I noticed that in other channels when they notice an issue/error in their videos, the correction or the link to correction they put under the description of the video. This is because not everybody looks to the comments, so they might miss it. What you did is also fine, but then probably would be good to pin the comment so that it would be always on the top.
2) Instead of putting the image in google drive, in which case you might need to provide access to viewers manually, you can add this image directly in the Community section of your channel. For this hit the Create button (video camera icon on top right) and do create post.
Hope this helps :)

[@circuitimage]

@@hrachya_khachatryan Thank you so much for your suggestions. All are so well that I applied all of them. I really appreciate your help when I made a mistake. I felt we are on the same team. 😀

[@quocphule6118]

Thank you from Japan

[@circuitimage]

Hi Quốc, nice to meet you. You are very welcome.

[@rangababuganta7725]

Thank you Chen

[@circuitimage]

Hi Rangababu, you're very welcome.

[@DDjadure]

Schematic 看起來有問題🤨 VCSN那點有兩個wide swing cascode diode connection 看起來怪怪的, 然後LOD effect 要不要斷OD 其實不同process 有差, 像是台積15年ASSCC 發表的12nm FinFET BGR 就有提出一種stack current mirror 不用dummy 的畫法, 核心概念是利用stack device 被壓死的那些對delta VGS ( ~= delta Vth)的變insensitive. 念phd 到現在發現analog 最麻煩的地方就是一堆process related know how 在學校根本沒人會…

[@circuitimage]

Hi Chieh-Ju, 很高興見到你、非常感謝你的反饋與指正。非常抱歉，我昨天畫圖的時候沒有注意到。我目前不知道如何在影片上更正?只能在留言區把正確的圖貼給大家，謝謝大家的諒解。也感謝🙏你的寶貴意見、你說的沒錯: "Analog有很多種不同的特殊狀況或是技巧"、所以，大家都要持續的學習、活到老學到老😄這也是我Circuit Images頻道的主要目的: 希望能夠跟大家一起討論、 不但幫助大家能夠進步也幫助我能夠學習到更多的東西💪最後我非常同意對於有些電路技巧的確不需要dummy。感謝你的意見，之後我也會做出相關的影片讓大家了解一下。感恩🙏

[@DDjadure]

@@circuitimage 頻道主學經歷看起來是很厲害的學長！ SerDes 部分給了我很多啟發, 自從Jri Lee 老師不開SerDes的課後, 台灣已經很少見有人能夠分享這麽多SerDes相關的knowledge了, 我只是路過剛好發現這個很厲害的頻道, 順便小小抱怨一下現在在台大作Analog/mixed signal的碩博都被先進製程搞的很煩 😂 希望別介意

[@circuitimage]

@@DDjadure 再次非常感謝🙏你寶貴的意見與反饋、我非常希望聽到各種不同的意見。這也是這個頻道的另外一個目的。除了我希望能夠，把我多年學到的SERDES 經驗傳授給其他人，也希望其他人能夠把他們遇到的問題、反饋讓我知道。所以，我並不認為這是抱怨😄而是非常寶貴的經驗😊。謝謝你的分享🙏我希望能夠聽到更多大家不同的聲音😄

[@ykhsieh7395]

這頻道很用心

[@circuitimage]

Hi yk, 很高興見到你、 非常感謝你的反饋😄