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Hi ToS, you're very welcome. :)

Glad you enjoyed it 🥰

Hi OSeyedian, nice to meet you. Thanks you so much for your feedback and I'm glad information was valuable to you. :)

Hi Green tangle, nice to meet you and thanks for the suggestions. I'll do the ADPLL. But I had a few VCOs here: 1. LC VCO Multiphase: th-cam.com/video/J0bKPaAbvxU/w-d-xo.html 2. Feed-forward Delay Cell for A Ring-based VCO: th-cam.com/video/kqL3HRjlums/w-d-xo.html 3. Multiphase VCO for An NRZ or PAM4: th-cam.com/video/lnj6xSTLuOI/w-d-xo.html Please let me know what else you need

Hi Lab_mangement, thanks for the feedback and I'm glad that you liked it. :)

Hi Greywhittef, Thanks for the good suggestions and I'll do it. :) Thanks, CC

Hi Joseph, Thanks for the good questions. I have comments below. What are the practical pros and cons of impulse response simulation vs numerically calculating the difference between two step response (a positive and negative step response) simulations? [CC] Are you asking about the correlation between the single-shot align with the two step responses? If yes, my understanding is that it should be equivalent if both responses don't saturate the system, which only assumes the passive elements of the lossy channel. :) Thanks, CC

Hi SUMAN, Thanks for the good questions. I have comments below. Thanks for the video. I have a question. The minimum amount of Swing at the Slicer input is decided by "BER/Slicer input noise/Sensitivity/offset" ? What limits the max side? Can we have very High Swing at the Slicer input for both High and low frequency components of the signal? [CC] The maximum swing may distort the linearity of the summing amplifier and then the DFE might not work well. In addition, there's a reliability issue if the maximum swing was not considered in the design. @1:40 : You tell for less dynamic range , sampling accuracy be increased or clockJitter power requirement is reduced? Can you explain in some more detail? [CC] The less dynamic range may help mitigate the sampler's hysteresis and perform faster with a less clock to Q or input setup time. Then the clock requirements of the sampler can be reduced. Thanks, CC

Hi 育瑛,Thanks for the feedback.🙏 Your understanding for the whole PLL loop operation is correct. 😊

@@circuitimage Thanks for the prompt reply!!

Hi Lab_mangement, thanks for your feedback. Yes, the eys is is very important for measuring super high Speed data analysis. :)

👍👍😔​@@circuitimage

Hi Christiane, thanks for feedback.

Hi Patricia, thanks for the feedback. :)

Hi Melissa, nice to meet you and thank you for feedback. :)

Hi Eric, nice to meet you. :)

Hi Kobe, thanks for the good question. The big DAC could have lots of parasitic on the high speed routing.

@@circuitimage CC,thanks for your reply,

@@KobeJames-ii4lz You're very welcome. :) Have a nice weekend!!

Hi @arnaud.lancelot, thanks for the feedback. Could you please elaborate on your concern?

@@circuitimage If the diff pair acts like an integrator, the gain has the form of gm/C. The input noise is (kt/C) /(gain x gain) . So input noise should look like kTxC/(gm x gm). So boost the gm transconductance for sure but diminish the capacitance C.

@@arnaud.lancelot I agree. So, in my video, I mentioned, the bigger C the less noise, but the speed goes down.

@@circuitimage What i m saying is that you should look at the SNR, signal to noise ratio. The smaller the capacitance, the lower the noise from... the input perspective. So you increase the SNR at the input. But you also increase it at the output (gmxgmxVxV/CxC)/(kT/C) ~1/C So you reduce C. you go faster and has a better SNR. Reducing the noise is useless if you reduce even more the signal gain.

@@arnaud.lancelot Thanks for the feedback, 🙏 and I agree with your SNR, which should match the input referred noise, which is the ouptut noise/gain, not just noise itself. 🎉😊

Hi Ahmad, Nice to meet you and thank you 🙏 for your questions. Since the channel frequency response was not equal loss over frequency, so we need to equalize it. 😊

@@circuitimage channel frequency response loss didn't equal the which frequency?

@@NostalgiaT Ideally, you want the gain is the same over your interested frequency, which is flat. But a lossy channel isn't flat.

@@NostalgiaT This CTLE th-cam.com/video/zsuJMqadaKY/w-d-xo.htmlsi=vpxIC-vZPHHTYV3d may show it.

Hi Ahmad, Nice to meet you and thank you 🙏 for your questions. Lots difference and you might want to check all my videos😊

Thank you!!

Hi Hanyue, Nice to meet you. Thanks for the good suggestion. Yes, that's correct. The 3D packaging helps the implementations of the Chiplet. Thanks, CC

Hi Shivangi, Nice to meet you. Thanks for the good feedback. The 5GHz would be the Nyquist rate of 10Gbps. Thanks, CC

​@@circuitimage Thanks for your response... But it would be quite helpful if you can explain this..I am a bit confused

​@@betu1207 Hi Shivangi, Sure. The simplest way of thinking about this is taking the maximum transition from any data pattern is the clock pattern, which is 1010. For example, the 1UI of the 10Gbps is 100ps, but the 1010 or clock pattern is 5GHz since the clock period is 200ps instead of 100ps or 50ps, so 5GHz is the Nyquist rate of the 10Gbps.

Hi Kobe, sure. Nice to meet you. :) Is this ( th-cam.com/video/YsFg_ReBBzQ/w-d-xo.html ) you're looking for?

Hi Abhirup, Thank you 🙏 so much for your feedback, which I agree with a lot. My PCI-Gen5 32Gbps also applied PLL's 16GHz clock.😊 I'll put your comments in my next video: "Why half-rate or quarter-rate DFE." 😊

@@circuitimage great, look forward CC.

@@abhiruplahiri1 Thanks for your always support. :)

Hi 장구, Nice to meet you. Thank you 🙏 so much for your feedback, which I agree with a lot. I'll put your comments in my next video: "Why half-rate or quarter-rate DFE." 😊

Hi Matthew, Nice to meet you. Thank you 🙏 so much for your corrections and for looking carefully, accidentally adding extra "the of".

Hi Pran, nice to meet you and thank you for the suggestions. Is this (th-cam.com/video/BZLVH-8JFys/w-d-xo.htmlsi=vhs3nMSafdXXshHz) you're looking for?

Hi Yifeng, thanks for the question. Could you please elaborate on which time your refer to?

Hi Lab_mangement, you're very welcome. :)

Hi PeiLife, you're very welcome.

Hi 树多多, you can check my video: Why Strong-arm Latch w/ An Optimized RS Latch to Meet Digital Timing? th-cam.com/video/vMWY41DADFc/w-d-xo.htmlsi=R2mkHLYYmrRiC9P3

@@circuitimage thanks!

@@树多多 ur very welcome. :)🥰

Thank you so much.

I guess the point is duty cycle in FR sampling can eventually be sensed as an error and corrected for by the loop. Such impairment worsens the ber even in FR, but in HR the duty cycle error on half rate clocks may not even be sensed (eg A goes to left, B to right but T is aligned) leading to higher uncorrected error and thus higher ber. I let CC comment more and enlighten us.

Hi Xiaodong, Thank you so much for the good questions. Also, thanks for the Abhirup's very good feedback, which aligns with what I tried to say. The duty-cycle distortion (DCD) may have a BER impact on all CDR no matter which topology or clock rate; therefore, we must do the duty-cycle correction (DCC) in another loop. The FR sampling's data & transition sample usually has a better DCC than the HR; therefore, the DCD of the FR is usually less. But adding a good design of DCC in the HR still can minimize the DCD as much as possible.

Hi Abhirup, thanks for your very good feedback, which aligns with what I tried to say. :)

@@circuitimage many thanks CC. Always looking forward to your interesting videos.

Hi Surya, Thank you so much for the good questions. I have comments below. Great.....can you please explain a bit more on how you choose the coefficient values of Pre and Post cursor taps. [CC] I did the a single-pulse response to figure out the coefficients of Pre and Post cursor, respectively. And 2nd doubt is can we see any case where you keep both the coefficient to be positive and in that case if the transition parts will have higher swing or lower ? [CC] Yes, that's possible. We only focus on the data parts, but the transition parts could have a higher swing or lower due to the reflection. Thanks, CC

Hi Ryan, I'm glad this helped you again. :)

Hi XX, Nice to meet you and you're very welcome. I have comments below. have two questions: 1. Are there any recent products of TSPC FF being used in the industry? [CC] Yes, that's a lot. 2. Samsung presented a new TSPC FF design in the VLSI symposium 2024, “An Area-Efficient True Single-Phase Clocked and Conditional Capture Flip-Flop for Ultra-Low-Power Operations in 7nm Fin-FET Process” but it seems like a static FF instead of a dynamic one. From the viewpoint of ultra-low voltage operation capability(~0.2V), energy consumption, and robustness, which is preferable? [CC] Unfortunately, IEEE has not put in online yet and I cannot check the paper. Would you mind sending it to me or share in your sharepoint? Thanks, CC

@@circuitimage Thank you so much for your reply. Here is the link to the paper: vlsi24.mapyourshow.com/mys_shared/vlsi24/handouts/C25.2_Thu_Hwang.pdf

@@circuitimage Thank you very much for your reply! I can't send you the Google Docs sharing link successfully. I guess the comments with links are automatically blocked in your channel settings. You can check whether Comment->Community->Automated Filters->Block Links is checked.

the paper link: drive.google.com/file/d/1kWNMA77yZmEInZci1twO1B7JAaringy-/view?usp=drive_link

​ @xxw6371 Thank you so much for the paper, which is very promising. But I'm not sure if that's really robust enough. 1. The input is not single-ended as the traditional TSPC 2. The differential signaling is good for PSRR, which might not be needed, but it adds the mismatch concerns. 3. Lots of elements of their LCFF may have more leakage and lots of parasitic than the traditional TSPC

Hi MrNonamel, nice to meet you and thanks for the good question. 😊 From power perspective, quarter-rate clocking is lower than the half-rate, and the half-rate is lower than the full-rate. But, the assumption is those phase correction or DCC and the complicated multi-phase routing is manageable in layout and design. :)

@@circuitimage DDR5 DRAM divide CK clock by 2 to achieve quarter-rate clocking, I wonder if this is due to speed or power reason?

Hi MrNonamel, Thank you so much for the good questions. I have comments below. DDR5 DRAM divide CK clock by 2 to achieve quarter-rate clocking, I wonder if this is due to speed or power reason? [CC] Both 😉 In addtion, the quarter-rate clocking in DDR5 DRAM would reduce the EMI (Electromagnetic Interference) challenges & SI issue, which also related to cost. 😊 Thanks, CC

Hi Abhirup, thanks for the reminder. I'm kind of implying it at the last Why half rate SerDes and this Serilaizer TX (if good RJ/DJ from the full-rate is doable in slide #2). :)

@@circuitimagemany thanks CC. Kudos to you for sharing such great information.

@@abhiruplahiri1 Thank you so much as well 🙏for your valuable feedback, which helps me improve the shared info and benefits other people in this IC design society. 😉

Hi Gman, nice to meet you. Good question. It's differential uncorrelated 5.2mV RMS noise. :)

Hi Viet, nice to meet you and thank you for your suggestions. I'll do a video about Frequency divider using CML Flip Flop. :)

Hi Analogue, nice to meet you, and thanks for the feedback. Yes, we'll also show the drawback of the half-rate or quad-rate clocking later. :)

Hi Syed, nice to see you and thank you for the feedback. I'm happy it helped you. :)

Hi layt01, nice to meet you and thank you for your feedback. I'm glad you liked it. :)

Hi Abhirup, thanks for the nice feedback. Your experiences match what I have. My understanding is the NRZ up to 32Gbps, the ring VCO is already good enough, but not good enough for the PAM4 SerDes above 56Gbps. Therefore, the :2 LC VCO with good phase noise is Challenge. :)

@@circuitimage thanks for the input CC.

@@abhiruplahiri1 you're very welcome. :)

Hi Zixiang, thanks for the feedback and nice to meet you. I'm glad you liked it. :)

HI Allen, thanks for the feedback.

Hi Layout_books, 非常感谢🙏😉

Hi HubbA, Thank you.

@@circuitimage I encourage you to continue, but what I would like is to solve problems, but from the basics, you. It has very advanced concepts, it should be created as a course, in which it would give the possibility of getting at their level, VD. MUST teach (teacher :), ! I follow him :), greetings from Spain

@@k4r4m310. Hi HubbA, Thank you for your encouragement and suggestions. I'll keep going and try to make a course for everyone. Likewise, I may think about writing a book for everyone if time is allowed. :)

@@circuitimage do it yourself , hágalo vd. un cordial saludo