Avoid Bad Design Guidelines with Eric Bogatin | OnTrack Podcast with Zach Peterson

Our podcast all-time favorite podcast guest is back to help PCB designers recognize bad PCB design guidelines. Tune in and listen on the go now. This is a fun and insightful episode! Watch until the end, our favorite Dean has some perks for our listeners.
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#weengineertogether

[@chrisbradley3224]

The 0.1 uF cap is apparently magic. If I don't use a 0.1 uF cap on an IC and use a different value I am guaranteed to get at least one person asking where the 0.1 uF cap is.

[@asmi06]

On a subject of bit flips - I think it's just our brains are not good with very large and very small numbers. If you ask somebody if 1 to 1B chance event is likely to happen, they will most certainly say "no", but when you have a relative slow by modern standards gigabit line, 1:1B error rate means that an error happens every *second* (on average)!

[@robertdixon8238]

Thanks Eric and your colleagues for exposing myths and legacy code. Have you approached component manufacturers to get them to fix datasheets and app notes? It's about time the source of the split planes was finally fixed.

[@Zachariah-Peterson]

Hi Robert,
I can't speak for Eric but I can say something about design guidelines in datasheets and app notes. The board layout guidelines you might see in datasheets are normally mirrored from specific test boards or evaluation products. So the manufacturer is really only telling you that the circuit/component worked in their specific situation, they can't guarantee the component will work in every situation. This is why you keep getting the ferrite bead on power lead guidelines all over the place. It works in certain situations but it makes high frequency noise worse in other situations, and yet the guideline was probably developed for a totally different situation. So in that sense, the guidelines aren't universally wrong if your only metric for success is to ensure you get a working circuit, but that doesn't mean the circuit will be low noise or pass EMC.

[@AveyaC2012]

Fantastic 😍 well done friend, Thank you for sharing.✨💖

[@AltiumAcademy]

Thank you! Cheers!

[@davidvanhorn498]

The enemy of proper design: (12 minute mark) "But it works"... :) Can't tell you how many designs I've had to re-design because the previous designer assumed that since it worked on his single prototype, we could build 1,000,000 of them without excessive failure rates.

[@waleedarshad8160]

Thanks for this!! BTW the promo code to the 3-month subscription is not working, could you please let me know if it's valid. I was really looking forward to that. Thanks

[@Zachariah-Peterson]

I just sent an email over to Eric to verify that this is correct, I'll follow up ASAP

[@waleedarshad8160]

@@Zachariah-Peterson Thanks Zach, appreciate your response!

[@petersage5157]

How important is any of this for frequencies (including intentionally introduced diode or *FET/triode/pentode distortion) in the audio domain, assuming anything over 16KHz is snubbed to ground? My primary interest in electronics is analog musical instrument amplifiers and distortion pedals; in this frequency domain, isn't it more helpful to exploit and encourage parasitic capacitance and inductance that we generally avoid in the digital domain? H E double hockey sticks, many distortion pedals have RC treble shunting on the output that swamps any "pathological design" parasitic capacitance by many orders of magnitude.

[@Zachariah-Peterson]

This stuff with grounding and parasitics is a lot more important in instances where: 1) you're operating with typical digital ICs, and 2) you're working with very low signal levels, like micro-volts. In the first case you're at higher frequencies, but you get the most benefit and ease of routing when you put the GND plane below the signal layer, and ideally as close to the signal layer as possible. In the latter case you could be working at any frequency, so it would also apply in analog measurements at audio frequencies. In that case where you are taking low-level analog measurements, you would also use a lot of filtering, isolation with splitting up planes and adding a lot of stitching around signal paths.
Also you're right, an intentionally placed cap or RC circuit will beat parasitic capacitive impedance hands down, that's one reason we might place a cap across PGND and SGND on a transformer. The intentionally placed capacitor will be the signal path rather than the winding capacitance across the TX as long as the placed cap is larger capacitance than the parasitic.

[@pawanmarathe5907]

Can you share mail id. I need one help in high speed design pcb

[@VeritasEtAequitas]

Good overview of the concept, but I expected many real examples to be explained

[@pravinsengottaiyan9244]

How to review pcb?
Please share video link

[@Zachariah-Peterson]

Hi Pravin, that's a great idea for a video, I'll put it on my list to create over the holiday break!

[@pravinsengottaiyan9244]

@@Zachariah-Peterson Thanks a lot.Its helpful for us.🙏😊