Synthesis/STA - virtual clock concept

[@PINTUKUMAR-rv8po]

one of the best lecture on youtube

[@VLSI-learnings]

Thank you

[@saikumarpilla6271]

Hi sir
U have doubt For combinational paths we have constraint like set_max_delay delayvalue -from [all_inputs] - to [all_outputs] for setup and set_max_delay delayvalue -from [all_inputs] - to [all_outputs] for hold.
Why can't we give this constraint?

[@shiva7870]

Hi, if we use virtual clock in the design, which type of hardware will inferred ??

[@VLSI-learnings]

Virtual clock mean tool is assuming there is clock .. but physicaly that clock not present in design

[@pravin5566]

Hi Sir,
Mostly input-output delay on ports are set as 60-40% of clock period, why ?

[@UDonotKnowMeBecauseUKnowMe]

thank u.
it is much helpful.

[@VLSI-learnings]

Welcome

[@VRL369]

Sir very well explained thanks
I have a doubt why do some inputs are not provided witj clocks?

[@VLSI-learnings]

Thank you

[@lokeshrahul3893]

what happens if i set master clock in set_input_delay -clock -ports [get_ports A]

[@prasadgadipalli7077]

Yes , I have also same doubt , why can't we use the real clocks ?

[@sathyasuthanthra]

I have one doubt sir, i have two signals one scl,sda these signals is depends on master. i have connected in port in these signals. so how I declared delay in sda line with respect to scl it's possible or not?two signals are connected in port but one clock another one data it is output of master directly .

[@rohanyadala9096]

Hi sri, why don't u make more videos

[@VLSI-learnings]

Sure

[@omprakashchoudhary4901]

sir can u explain all that STA analysis using any open-source tool ..........in the industrial manner

[@VLSI-learnings]

It not possible .

[@pgvinaykumar9196]

Good explanation sir

[@VLSI-learnings]

thank you.. keep watching my videos

[@kvenkatamohanreddy1223]

good explation thank u .....

[@VLSI-learnings]

Thank you