i know i have exam tmr and i know i still have alot to prepare but i want to pull a couple of secs to thank this human for literallly helping me in every subject !
Indian government should pay to sir to provide these kinds of informative videos provided free of cost by sir which are very very helpful to those students which are financialy weaker to take choching classes and this sir provided very very nowledegable videos which can't be provided by any choching institution.
@@anusharapaka2413 clock is not an output it is used to enable the FF also the clock can have different timeperiods hence by considering it as LSB we will get wrong answer
+GunZTube1 yes we can. T flipflop is simply tying both the J and K inputs together internally. One can always use JK flip flops and connect the inputs separately to "1" or tie them together to "1"(like the earlier presentation)
I cannot understand how can a d flip flop make such toggling effect? as far as I understand that we have d as logic high (1) and the clock is toggling between 0 and 1. for each negative edge Q should be equal to d which 1 so Q should be always high logic 1 not toggling. Can you please correct me if I am wrong and explain the concept behind that toggling effect?
you can use j-k flip flop like in previous video. It does not matter. T flip flop is actually like giving same inputs to j-k flip flop i.e if u give same input to a j-k f.f lets say 'x' then it behaves like 't' flip-flop. So in the end we are giving '1' as input in the flops
Sir, i hv a confusion about the usage of clock pulse in up counters and down counters in asynchronous and synchronous counters. When we use Q as an output then Which kind of clock pulse (either positive edge or negative edge) we must use to make up counter (in asynchronous and synchronous counters) ???? When we use Q complement, as an output then Which kind of clock pulse (either positive edge or negative edge) we must use to make down counter (in asynchronous and synchronous counters) ?????? Why the negative edge clock pulse is used all the time. If we use positive edge clock pulse then how to draw the time diagram ???
Bhanupriya Soni For Asynchronous If it is Q compliment and positive clock then it is up counter. And if it is negative clock then down counter And for Q if it is positve clock then down counter. And if it is negative clock then up counter
Why dont we clock as the lowest bit output? That can save us the use of one flip flop and will increase the speed by a factor of 2 ?? Cheaper and more efficient ,
I am grateful to have people like you on TH-cam ...Blessed to have you
i know i have exam tmr and i know i still have alot to prepare but i want to pull a couple of secs to thank this human for literallly helping me in every subject !
The best thing about this series is that the videos are short and clear cut all imp points are explained❤️❤️
This is a tremendous approach for learning key n core concept.Never ever I had experience and learn this subject in such an easier way. Thanks a lot.
nice explanation.
what i couldn't understand in three 1 hour lectures ,i got it cleared in 10 min
You helped me fetch good marks in my university exams.Thanks for this videos sir!!You are really doing a wonderful job
Happy Teacher's Day Sir
?
Such a pleasure to have you in platform like TH-cam...
Indian government should pay to sir to provide these kinds of informative videos provided free of cost by sir which are very very helpful to those students which are financialy weaker to take choching classes and this sir provided very very nowledegable videos which can't be provided by any choching institution.
It can't be any better. Perfect explanation of 4 bit asynchronous up counter.
what an excellent well layout explanation, sir keep up the good work :D
Sir very helpful Explanations
thank you so much for the videos, I am a student at MSU Denver EET
such a great explanation sir....
this guy is just amazing!
I don't know how to thank you, best explanation
Sir very good explanation
this is gold for us students.
Your indian accent makes the videos more enjoyable to watch xD
Lol what's wrong with that
yes. i also want to know@@Nobodyxu987ui
You guys are a life saver!!!❤️❤️
This is what we call a ripple counter right ?
Yes
very thankful to you sir
telugu lo antaru mamsam ni neesu. I love neso
Thanks a lot ! you made it easy and very clear to me
how do you write from the mouse so fast
It is easy to understand tq sir
Can we use JK flip flop for 4 bit asynchronous up counter ?
Thanks for giving this presentation on counter this acedmy is best from online revolution is occure
Nice explanation.
End Term prepration ON :}
Thanku for wonderful explanation
Sir, I’ve a question what if we use clock as LSB and Qd as MSB then we’ll have 5 outputs and this will count upto 31. Is it possible?
You cannot obtain a regular count like that
Yes same doubt..
By using 5 bit up counter can't we achieve 31 counts
@@anusharapaka2413 clock is not an output it is used to enable the FF also the clock can have different timeperiods hence by considering it as LSB we will get wrong answer
Can we use positive edge triggered for asynchronous counter?
how can i do an asynchronus up counter using jk flip flop ?
Just replace T-flip flops with JK flip-flops, that's it.
so Asynchronous meaning clock from pulse generator is only given in first FF? and Synchronous meaning clock from pulse generator is given to all FF?
Very Good yaar nice videos
why can't we use T flip flop for 3-bit ripple counter?
why do we use toggling mode..?
Sir, can we still use JK flip flops like the last presentation?
+GunZTube1 yes we can. T flipflop is simply tying both the J and K inputs together internally. One can always use JK flip flops and connect the inputs separately to "1" or tie them together to "1"(like the earlier presentation)
yes
What if I put my nose to the grindstone and present a up down counter that counts at the low to high or high to low transition??
we use counters only for those flip flops which makes the use of toggling?
what if we connect a positive edge triggered?
I need timing diagram for synchronous counters
Sir how to count the unused state of the flip flop.
what happens when we apply positive triggering
The toggling will take place at the the LOW to High part of clock , so the waveform will shif left by T/2
output will be same as negative triggering for use of positive triggering instead of negative triggering?
Output is not predictable when you use positive triggering because of the race around condition
just give the complement of Qn as the clock of the (n+1) flipflop
Sir, why do we take only the falling edges in case of counter? Hope to get a reply.
We can take leading edge also.. but clock pulse should be from Qn'(dash) instead of Qn
Thank you sir!
can we construct a 3 bit asynchronous counter with the help of t ff similar to 4 bit?
yes, we can use T-Flip Flops in a 3-Bit counter. We just need the toggling which is provided in both of these cases of flip flop.
PLZ REPLY SIR!!!
In 3 bit/4 bit asynchronus down counter why you have not connected preset and clear???
its just a schematic diagram, but for actual diagram we need to add it , nothing fancy :p
ty
sir,in the above table can we take QA QB QC QD instead of QD QC QB QA.
yes you are right but nesco is academy isnt wrong
In the case 4bit should we draw the line upto 16
If I draw upto 8,is it a mistake.
please make video on 8 bit up down counter
So we can't use jk flip flop?
i thought Qn+1 = D for a D flip flop. why is there toggling ?
This is a T flip flop which is just a J K flip flop with the inputs tied together (the input is always the same for J and K)
Tq so much sir its very usefull
what if we use positive edge triggered clock
Use jk flip-flop and from clock signal from one to to another is taken from qn' instead of qn
please make a video on 4bit synchronous down counter
Sir...... Why counter worked at toogle state🤔
I cannot understand how can a d flip flop make such toggling effect?
as far as I understand that we have d as logic high (1) and the clock is toggling between 0 and 1. for each negative edge Q should be equal to d which 1 so Q should be always high logic 1 not toggling.
Can you please correct me if I am wrong and explain the concept behind that toggling effect?
He's using T ff not D ff
What's the diagram for asynchronous down counter for t flip flop
how the 1 and 0 changing in the circuit
sir why you have used T flip-flop not J-K flip-flop?
Ashish Ranjan bcz we want only toggling action that's why we use T ff
you are amazing, but i still dont get how can you toggle using d flip flop
Sir,,,,can I use JK flip flop in this case?
yes
if T FLIPFLOP IS USED IF T=1 THEN J=1 AND K=1
please upload synchronous down counter
sir i have a question , in the counter you use negative clock pulse why you use only negative clock pulse? can i use positive clock pulse?
It is negative edge triggered...and it will help us to avoid race around condition
Why we are using t flip-flop for 4 bit asynchronouus counter
you can use j-k flip flop like in previous video. It does not matter. T flip flop is actually like giving same inputs to j-k flip flop i.e if u give same input to a j-k f.f lets say 'x' then it behaves like 't' flip-flop.
So in the end we are giving '1' as input in the flops
why we are considering only -ve edge triggering for jk and T flip flops......????
It's very hlpful sir❤
Verry useful informations . Thank you a lot !
How To enable a four bit asynchronuous up counter?
Sir, i hv a confusion about the usage of clock pulse in up counters and down counters in asynchronous and synchronous counters.
When we use Q as an output then Which kind of clock pulse (either positive edge or negative edge) we must use to make up counter (in asynchronous and synchronous counters) ????
When we use Q complement, as an output then Which kind of clock pulse (either positive edge or negative edge) we must use to make down counter (in asynchronous and synchronous counters) ??????
Why the negative edge clock pulse is used all the time. If we use positive edge clock pulse then how to draw the time diagram ???
Bhanupriya Soni
For Asynchronous
If it is Q compliment and positive clock then it is up counter.
And if it is negative clock then down counter
And for Q if it is positve clock then down counter.
And if it is negative clock then up counter
I need the circuit explanation ....sir for counters .... instead of explaining wave forms
Thnq Very much.... 😀
Sir can we use T ff for 3bit up counter?
what is logic 1 and logic 3
logic 3??
Is this same for all the flip flops..Cause I saw some materials doing d flip flop in a different way.. can you explain please...
Sir if I use JK flip flop is there any issue in that?
A T ff is just a short circuited version of a JK ff so no it's fine
Can I please create perfect hindi subtitles for your videos
What will be difference if we use here jk flip flop instead of t flip flop
Thank you sir
Can we use JK flipflop for this 4 bit counter and is the output same as the t flip flop??
J=K=1. Using T flipflop will give the same result as T flip-flop is nothing but JK FF with J=K
Sir!, Which application you are using to teach, please tell me?
Power point I guess
Thank you!
Why dont we clock as the lowest bit output? That can save us the use of one flip flop and will increase the speed by a factor of 2 ?? Cheaper and more efficient ,
Why we are qb falling edge 3 rd line
why are you using the word toggling in this , please answer
Can T FF be used in 3 bit asynchronous Up counter?
Yes, because we require only the toggling condition (where J=1 AND K=1).
kindly tell me what is mode counter .
can we use JK instead of T Flip Flop
Yes We can, but as we only require the toggling condition we can use T=J=K =1. ie T Flip flop , which is more convenient
We have to give Qa' to clock of B and so on...That will give the UP counter
V nice sir... Can v design 3 bit counter with T flip flop?
Yes, you can.
this is using t flip flops?
It doesn't work on my Microcontroller with T FF. Have any Idea why? Same config no variable, it counts not in order obviously...!
Bro pls any video on 4 bit ripple down counter?? Iam not getting
thanks,,,where from you dear??
What does state mean?
Jai shree ram♥️
I enjoy these. W.
Sir plz explain 1K×1 SRAM Organisational